2008-08-13 20:19:35 +00:00
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///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the FastISel class.
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//
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//===----------------------------------------------------------------------===//
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2008-08-19 22:31:46 +00:00
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#include "llvm/Instructions.h"
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2008-08-13 20:19:35 +00:00
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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2008-08-20 00:11:48 +00:00
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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DenseMap<const Value*, unsigned> &ValueMap) {
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unsigned Op0 = ValueMap[I->getOperand(0)];
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unsigned Op1 = ValueMap[I->getOperand(1)];
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2008-08-20 00:35:17 +00:00
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if (Op0 == 0 || Op1 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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2008-08-20 00:11:48 +00:00
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
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if (ResultReg == 0)
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// Target-specific code wasn't able to find a machine opcode for
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// the given ISD opcode and type. Halt "fast" selection and bail.
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return false;
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2008-08-20 00:23:20 +00:00
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// We successfully emitted code for the given LLVM Instruction.
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2008-08-20 00:11:48 +00:00
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ValueMap[I] = ResultReg;
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return true;
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}
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bool FastISel::SelectGetElementPtr(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap) {
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// TODO: implement me
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return false;
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}
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2008-08-13 20:19:35 +00:00
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BasicBlock::iterator
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2008-08-20 18:09:02 +00:00
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FastISel::SelectInstructions(BasicBlock::iterator Begin,
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BasicBlock::iterator End,
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2008-08-13 20:19:35 +00:00
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DenseMap<const Value*, unsigned> &ValueMap) {
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BasicBlock::iterator I = Begin;
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for (; I != End; ++I) {
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switch (I->getOpcode()) {
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2008-08-20 00:23:20 +00:00
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case Instruction::Add: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::Sub: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::Mul: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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2008-08-20 00:11:48 +00:00
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case Instruction::SDiv:
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if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
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case Instruction::UDiv:
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if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
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case Instruction::FDiv:
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if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
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case Instruction::SRem:
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if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
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case Instruction::URem:
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if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
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case Instruction::FRem:
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if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
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case Instruction::Shl:
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if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
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case Instruction::LShr:
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if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
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case Instruction::AShr:
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if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
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case Instruction::And:
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if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
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case Instruction::Or:
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if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
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case Instruction::Xor:
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if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
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case Instruction::GetElementPtr:
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if (!SelectGetElementPtr(I, ValueMap)) return I;
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2008-08-13 20:19:35 +00:00
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break;
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2008-08-20 00:11:48 +00:00
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2008-08-19 22:31:46 +00:00
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case Instruction::Br: {
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BranchInst *BI = cast<BranchInst>(I);
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// For now, check for and handle just the most trivial case: an
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// unconditional fall-through branch.
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2008-08-20 01:17:01 +00:00
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if (BI->isUnconditional()) {
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MachineFunction::iterator NextMBB =
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next(MachineFunction::iterator(MBB));
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if (NextMBB != MF->end() &&
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NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
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MBB->addSuccessor(NextMBB);
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break;
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}
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2008-08-19 22:31:46 +00:00
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}
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// Something more complicated. Halt "fast" selection and bail.
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return I;
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}
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2008-08-13 20:19:35 +00:00
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default:
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// Unhandled instruction. Halt "fast" selection and bail.
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return I;
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}
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}
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return I;
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}
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2008-08-14 21:51:29 +00:00
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FastISel::~FastISel() {}
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2008-08-13 20:19:35 +00:00
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unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
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return 0;
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}
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unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/, unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
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2008-08-20 18:09:38 +00:00
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const TargetRegisterClass* RC) {
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2008-08-13 20:19:35 +00:00
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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2008-08-20 18:10:48 +00:00
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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2008-08-13 20:19:35 +00:00
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2008-08-19 20:46:54 +00:00
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MachineInstr *MI = BuildMI(*MF, II, ResultReg);
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2008-08-13 20:19:35 +00:00
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MBB->push_back(MI);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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2008-08-20 18:10:48 +00:00
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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2008-08-13 20:19:35 +00:00
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2008-08-20 18:16:32 +00:00
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MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0);
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2008-08-13 20:19:35 +00:00
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MBB->push_back(MI);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned ResultReg = MRI.createVirtualRegister(RC);
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2008-08-20 18:10:48 +00:00
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const TargetInstrDesc &II = TII->get(MachineInstOpcode);
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2008-08-13 20:19:35 +00:00
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2008-08-20 18:16:32 +00:00
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MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0).addReg(Op1);
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2008-08-13 20:19:35 +00:00
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MBB->push_back(MI);
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return ResultReg;
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}
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