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llvm-6502/test/MC/ARM/arm_instructions.s

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ArmAsm
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Mark ARM subtarget features that are available for the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 16:59:54 +00:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
@ CHECK: nop
fix the asmmatcher generator to handle targets with no RegisterPrefix (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:42 +00:00
@ CHECK: encoding: [0x00,0xf0,0x20,0xe3]
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
nop
@ CHECK: nopeq
fix the asmmatcher generator to handle targets with no RegisterPrefix (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:42 +00:00
@ CHECK: encoding: [0x00,0xf0,0x20,0x03]
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
nopeq
Add encoding for ARM "trap" instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21 11:05:29 +00:00
@ CHECK: trap
@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
trap
fix the asmmatcher generator to handle targets with no RegisterPrefix (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:42 +00:00
@ CHECK: bx lr
@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
bx lr
most simple arm instructions match correctly now, it looks like we're not handling [] operands though git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117607 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:31:07 +00:00
@ CHECK: vqdmull.s32 q8, d17, d16
@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
vqdmull.s32 q8, d17, d16
Test encodings for LDM and STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16 01:38:20 +00:00
@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8]
@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9]
ldmia r2, {r1,r3-r6,sp}
ldmib r2, {r1,r3-r6,sp}
ldmda r2, {r1,r3-r6,sp}
ldmdb r2, {r1,r3-r6,sp}
@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9]
@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8]
@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
stmia r2, {r1,r3-r6,sp}
stmib r2, {r1,r3-r6,sp}
stmda r2, {r1,r3-r6,sp}
stmdb r2, {r1,r3-r6,sp}
Add support for parsing the writeback ("!") token. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 23:43:05 +00:00
@ CHECK: ldmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8]
@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
ldmia r2!, {r1,r3-r6,sp}
ldmib r2!, {r1,r3-r6,sp}
ldmda r2!, {r1,r3-r6,sp}
ldmdb r2!, {r1,r3-r6,sp}
@ CHECK: stmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8]
@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9]
@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8]
@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9]
stmia r2!, {r1,r3-r6,sp}
stmib r2!, {r1,r3-r6,sp}
stmda r2!, {r1,r3-r6,sp}
stmdb r2!, {r1,r3-r6,sp}
Add support for parsing ARM arithmetic instructions that update or don't update the condition codes. Where the ones that do have an 's' suffix and the ones that don't don't have the suffix. The trick is if MatchInstructionImpl() fails we try again after adding a CCOut operand with the correct value and removing the 's' if present. Four simple test cases added for now, lots more to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 19:19:43 +00:00
@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
and r1, r2, r3
@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
ands r1, r2, r3
@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
eor r1, r2, r3
@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
eors r1, r2, r3
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