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15 lines
542 B
LLVM
15 lines
542 B
LLVM
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; RUN: llc -march=arm64 < %s
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; The DAGCombiner tries to do following shrink:
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; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
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; But currently it can't handle vector type and will trigger an assertion failure
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; when it tries to generate an add mixed using vector type and scaler type.
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; This test checks that such assertion failur should not happen.
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define <1 x i64> @dotest(<1 x i64> %in0) {
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entry:
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%0 = add <1 x i64> %in0, %in0
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%vshl_n = shl <1 x i64> %0, <i64 32>
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%vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
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ret <1 x i64> %vsra_n
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}
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