2013-02-01 11:40:47 +00:00
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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2013-01-31 12:12:40 +00:00
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@var32 = global i32 0
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@var64 = global i64 0
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define void @test_zr() {
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; CHECK: test_zr:
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store i32 0, i32* @var32
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; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
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store i64 0, i64* @var64
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; CHECK: str xzr, [{{x[0-9]+}}, #:lo12:var64]
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ret void
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; CHECK: ret
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}
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define void @test_sp(i32 %val) {
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; CHECK: test_sp:
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; Important correctness point here is that LLVM doesn't try to use xzr
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; as an addressing register: "str w0, [xzr]" is not a valid A64
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; instruction (0b11111 in the Rn field would mean "sp").
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%addr = getelementptr i32* null, i64 0
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store i32 %val, i32* %addr
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; CHECK: mov x[[NULL:[0-9]+]], xzr
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; CHECK: str {{w[0-9]+}}, [x[[NULL]]]
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ret void
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; CHECK: ret
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}
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