2009-09-09 00:09:15 +00:00
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; RUN: llc < %s -march=arm -mattr=+neon > %t
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2009-06-22 23:27:02 +00:00
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; RUN: grep {vshll\\.s8} %t | count 1
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; RUN: grep {vshll\\.s16} %t | count 1
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; RUN: grep {vshll\\.s32} %t | count 1
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; RUN: grep {vshll\\.u8} %t | count 1
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; RUN: grep {vshll\\.u16} %t | count 1
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; RUN: grep {vshll\\.u32} %t | count 1
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; RUN: grep {vshll\\.i8} %t | count 1
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; RUN: grep {vshll\\.i16} %t | count 1
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; RUN: grep {vshll\\.i32} %t | count 1
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define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
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ret <2 x i64> %tmp2
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}
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define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
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ret <2 x i64> %tmp2
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}
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; The following tests use the maximum shift count, so the signedness is
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; irrelevant. Test both signed and unsigned versions.
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define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
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ret <2 x i64> %tmp2
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}
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declare <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
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