2012-02-18 12:03:15 +00:00
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//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
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2005-08-04 07:12:09 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-08-04 07:12:09 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2011-07-01 21:01:15 +00:00
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// This file implements the PPC specific subclass of TargetSubtargetInfo.
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2005-08-04 07:12:09 +00:00
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//
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//===----------------------------------------------------------------------===//
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2005-10-14 23:51:18 +00:00
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#include "PPCSubtarget.h"
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#include "PPC.h"
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2012-12-03 16:50:05 +00:00
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#include "PPCRegisterInfo.h"
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2013-07-15 22:29:40 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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2013-09-11 23:05:25 +00:00
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#include "llvm/CodeGen/MachineScheduler.h"
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2013-07-15 22:29:40 +00:00
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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2014-01-07 11:48:04 +00:00
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#include "llvm/IR/GlobalValue.h"
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2012-06-12 03:03:13 +00:00
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#include "llvm/Support/Host.h"
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2011-08-24 18:08:43 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Target/TargetMachine.h"
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2009-01-05 17:59:02 +00:00
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#include <cstdlib>
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2011-07-01 20:45:01 +00:00
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2014-04-22 02:03:14 +00:00
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using namespace llvm;
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2014-04-21 22:55:11 +00:00
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#define DEBUG_TYPE "ppc-subtarget"
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2011-07-01 20:45:01 +00:00
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#define GET_SUBTARGETINFO_TARGET_DESC
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2011-07-08 01:53:10 +00:00
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#define GET_SUBTARGETINFO_CTOR
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2011-07-01 22:36:09 +00:00
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#include "PPCGenSubtargetInfo.inc"
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2011-07-01 20:45:01 +00:00
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2014-06-12 21:08:06 +00:00
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/// Return the datalayout string of a subtarget.
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static std::string getDataLayoutString(const PPCSubtarget &ST) {
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const Triple &T = ST.getTargetTriple();
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std::string Ret;
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// Most PPC* platforms are big endian, PPC64LE is little endian.
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if (ST.isLittleEndian())
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Ret = "e";
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else
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Ret = "E";
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Ret += DataLayout::getManglingComponent(T);
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// PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
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// pointers.
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if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
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Ret += "-p:32:32";
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// Note, the alignment values for f64 and i64 on ppc64 in Darwin
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// documentation are wrong; these are correct (i.e. "what gcc does").
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if (ST.isPPC64() || ST.isSVR4ABI())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
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if (ST.isPPC64())
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Ret += "-n32:64";
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else
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Ret += "-n32";
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return Ret;
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}
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2014-06-12 20:54:11 +00:00
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PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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return *this;
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}
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2011-06-30 01:53:36 +00:00
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PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
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2014-06-12 22:50:10 +00:00
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const std::string &FS, PPCTargetMachine &TM,
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bool is64Bit, CodeGenOpt::Level OptLevel)
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2014-05-13 20:49:08 +00:00
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: PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
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2014-07-28 13:09:28 +00:00
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OptLevel(OptLevel), TargetABI(PPC_ABI_UNKNOWN),
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2014-06-12 21:08:06 +00:00
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FrameLowering(initializeSubtargetDependencies(CPU, FS)),
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2014-06-12 22:50:10 +00:00
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DL(getDataLayoutString(*this)), InstrInfo(*this), JITInfo(*this),
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2014-06-12 23:02:32 +00:00
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TLInfo(TM), TSInfo(&DL) {}
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2013-07-15 22:29:40 +00:00
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/// SetJITMode - This is called to inform the subtarget info that we are
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/// producing code for the JIT.
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void PPCSubtarget::SetJITMode() {
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// JIT mode doesn't want lazy resolver stubs, it knows exactly where
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// everything is. This matters for PPC64, which codegens in PIC mode without
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// stubs.
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HasLazyResolverStubs = false;
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// Calls to external functions need to use indirect calls
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IsJITCodeModel = true;
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}
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void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
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AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-cpu");
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Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-features");
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std::string CPU =
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!CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
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std::string FS =
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!FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
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if (!FS.empty()) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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}
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}
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2005-08-05 22:05:03 +00:00
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2013-07-15 22:29:40 +00:00
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void PPCSubtarget::initializeEnvironment() {
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StackAlignment = 16;
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DarwinDirective = PPC::DIR_NONE;
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HasMFOCRF = false;
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Has64BitSupport = false;
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Use64BitRegs = false;
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Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
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UseCRBits = false;
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2013-07-15 22:29:40 +00:00
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HasAltivec = false;
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HasQPX = false;
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[PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:58:58 +00:00
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HasVSX = false;
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2013-08-19 05:01:02 +00:00
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HasFCPSGN = false;
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2013-07-15 22:29:40 +00:00
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HasFSQRT = false;
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HasFRE = false;
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HasFRES = false;
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HasFRSQRTE = false;
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HasFRSQRTES = false;
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HasRecipPrec = false;
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HasSTFIWX = false;
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HasLFIWAX = false;
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HasFPRND = false;
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HasFPCVT = false;
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HasISEL = false;
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HasPOPCNTD = false;
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HasLDBRX = false;
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IsBookE = false;
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2013-09-12 14:40:06 +00:00
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DeprecatedMFTB = false;
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DeprecatedDST = false;
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2013-07-15 22:29:40 +00:00
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HasLazyResolverStubs = false;
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IsJITCodeModel = false;
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}
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void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
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2005-09-01 21:38:21 +00:00
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// Determine default and user specified characteristics
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2011-06-30 01:53:36 +00:00
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "generic";
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2012-06-12 03:03:13 +00:00
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#if (defined(__APPLE__) || defined(__linux__)) && \
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(defined(__ppc__) || defined(__powerpc__))
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2011-06-30 01:53:36 +00:00
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if (CPUName == "generic")
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2012-06-12 03:03:13 +00:00
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CPUName = sys::getHostCPUName();
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2005-09-01 21:38:21 +00:00
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#endif
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2005-10-26 17:30:34 +00:00
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2011-07-01 20:45:01 +00:00
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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2012-10-25 12:27:42 +00:00
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// Make sure 64-bit features are available when CPUname is generic
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std::string FullFS = FS;
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2006-06-16 17:50:12 +00:00
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// If we are generating code for ppc64, verify that options make sense.
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2013-07-15 22:29:40 +00:00
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if (IsPPC64) {
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2008-02-15 18:40:53 +00:00
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Has64BitSupport = true;
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2006-06-16 20:05:06 +00:00
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// Silently force 64-bit register use on ppc64.
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Use64BitRegs = true;
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2012-10-25 12:27:42 +00:00
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if (!FullFS.empty())
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FullFS = "+64bit," + FullFS;
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else
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FullFS = "+64bit";
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2006-06-16 17:50:12 +00:00
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}
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2012-10-04 16:20:24 +00:00
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2014-05-13 20:49:08 +00:00
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// At -O2 and above, track CR bits as individual registers.
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if (OptLevel >= CodeGenOpt::Default) {
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if (!FullFS.empty())
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FullFS = "+crbits," + FullFS;
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else
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FullFS = "+crbits";
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}
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2012-10-25 12:27:42 +00:00
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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2006-06-16 17:50:12 +00:00
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// If the user requested use of 64-bit regs, but the cpu selected doesn't
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2008-02-15 18:40:53 +00:00
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// support it, ignore.
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if (use64BitRegs() && !has64BitSupport())
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2006-06-16 17:50:12 +00:00
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Use64BitRegs = false;
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2006-12-11 23:22:45 +00:00
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// Set up darwin-specific properties.
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2009-08-11 22:49:34 +00:00
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if (isDarwin())
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2006-12-11 23:22:45 +00:00
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HasLazyResolverStubs = true;
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2013-01-30 23:43:27 +00:00
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// QPX requires a 32-byte aligned stack. Note that we need to do this if
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// we're compiling for a BG/Q system regardless of whether or not QPX
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// is enabled because external functions will assume this alignment.
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if (hasQPX() || isBGQ())
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StackAlignment = 32;
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2013-07-26 01:35:43 +00:00
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// Determine endianness.
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IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
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2014-06-05 16:21:13 +00:00
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// FIXME: For now, we disable VSX in little-endian mode until endian
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// issues in those instructions can be addressed.
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if (IsLittleEndian)
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HasVSX = false;
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2014-07-28 13:09:28 +00:00
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// Determine default ABI.
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if (TargetABI == PPC_ABI_UNKNOWN) {
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if (!isDarwin() && IsPPC64) {
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if (IsLittleEndian)
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TargetABI = PPC_ABI_ELFv2;
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else
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TargetABI = PPC_ABI_ELFv1;
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}
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}
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2006-12-11 23:22:45 +00:00
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}
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/// hasLazyResolverStub - Return true if accesses to the specified global have
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/// to go through a dyld lazy resolution stub. This means that an extra load
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/// is required to get the address of the global.
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2009-08-02 22:11:08 +00:00
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bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
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const TargetMachine &TM) const {
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2010-11-15 02:46:57 +00:00
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// We never have stubs if HasLazyResolverStubs=false or if in static mode.
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2006-12-11 23:22:45 +00:00
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if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
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return false;
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2008-12-05 01:06:39 +00:00
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// If symbol visibility is hidden, the extra load is not needed if
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// the symbol is definitely defined in the current translation unit.
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2010-01-27 20:34:15 +00:00
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bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
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2008-12-05 01:06:39 +00:00
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if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
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return false;
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2006-12-11 23:22:45 +00:00
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return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
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2008-12-05 01:06:39 +00:00
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GV->hasCommonLinkage() || isDecl;
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2005-08-04 07:12:09 +00:00
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}
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2011-12-02 04:58:02 +00:00
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Add a scheduling model (with itinerary) for the PPC POWER7
This adds a scheduling model for the POWER7 (P7) core, and enables the
machine-instruction scheduler when targeting the P7. Scheduling for the P7,
like earlier ooo PPC cores, requires considering both dispatch group hazards,
and functional unit resources and latencies. These are both modeled in a
combined itinerary. Dispatch group formation is still handled by the post-RA
scheduler (which still needs to be updated for the P7, but nevertheless does a
pretty good job).
One interesting aspect of this change is that I've also enabled to use of AA
duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark
results seem to support this decision (see below), and while this is normally
useful for in-order cores, and not for ooo cores like the P7, I think that the
dispatch slot hazards are enough like in-order resources to make the AA useful.
Test suite significant performance differences (where negative is a speedup,
and positive is a regression) vs. the current situation:
MultiSource/Benchmarks/BitBench/drop3/drop3
with AA: N/A
without AA: -28.7614% +/- 19.8356%
(significantly against AA)
MultiSource/Benchmarks/FreeBench/neural/neural
with AA: -17.7406% +/- 11.2712%
without AA: N/A
(significantly in favor of AA)
MultiSource/Benchmarks/SciMark2-C/scimark2
with AA: -11.2079% +/- 1.80543%
without AA: -11.3263% +/- 2.79651%
MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt
with AA: -41.8649% +/- 17.0053%
without AA: -34.5256% +/- 23.7072%
MultiSource/Benchmarks/mafft/pairlocalalign
with AA: 25.3016% +/- 17.8614%
without AA: 38.6629% +/- 14.9391%
(significantly in favor of AA)
MultiSource/Benchmarks/sim/sim
with AA: N/A
without AA: 13.4844% +/- 7.18195%
(significantly in favor of AA)
SingleSource/Benchmarks/BenchmarkGame/Large/fasta
with AA: 15.0664% +/- 6.70216%
without AA: 12.7747% +/- 8.43043%
SingleSource/Benchmarks/BenchmarkGame/puzzle
with AA: 82.2713% +/- 26.3567%
without AA: 75.7525% +/- 41.1842%
SingleSource/Benchmarks/Misc/flops-2
with AA: -37.1621% +/- 20.7964%
without AA: -35.2342% +/- 20.2999%
(significantly in favor of AA)
These are 99.5% confidence intervals from 5 runs per configuration. Regarding
the choice to turn on AA during CodeGen, of these results, four seem
significantly in favor of using AA, and one seems significantly against. I'm
not making this decision based on these numbers alone, but these results
seem consistent with results I have from other tests, and so I think that, on
balance, using AA is a win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195981 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-30 20:55:12 +00:00
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// Embedded cores need aggressive scheduling (and some others also benefit).
|
2013-09-11 23:05:25 +00:00
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static bool needsAggressiveScheduling(unsigned Directive) {
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switch (Directive) {
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default: return false;
|
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case PPC::DIR_440:
|
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case PPC::DIR_A2:
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case PPC::DIR_E500mc:
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case PPC::DIR_E5500:
|
Add a scheduling model (with itinerary) for the PPC POWER7
This adds a scheduling model for the POWER7 (P7) core, and enables the
machine-instruction scheduler when targeting the P7. Scheduling for the P7,
like earlier ooo PPC cores, requires considering both dispatch group hazards,
and functional unit resources and latencies. These are both modeled in a
combined itinerary. Dispatch group formation is still handled by the post-RA
scheduler (which still needs to be updated for the P7, but nevertheless does a
pretty good job).
One interesting aspect of this change is that I've also enabled to use of AA
duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark
results seem to support this decision (see below), and while this is normally
useful for in-order cores, and not for ooo cores like the P7, I think that the
dispatch slot hazards are enough like in-order resources to make the AA useful.
Test suite significant performance differences (where negative is a speedup,
and positive is a regression) vs. the current situation:
MultiSource/Benchmarks/BitBench/drop3/drop3
with AA: N/A
without AA: -28.7614% +/- 19.8356%
(significantly against AA)
MultiSource/Benchmarks/FreeBench/neural/neural
with AA: -17.7406% +/- 11.2712%
without AA: N/A
(significantly in favor of AA)
MultiSource/Benchmarks/SciMark2-C/scimark2
with AA: -11.2079% +/- 1.80543%
without AA: -11.3263% +/- 2.79651%
MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt
with AA: -41.8649% +/- 17.0053%
without AA: -34.5256% +/- 23.7072%
MultiSource/Benchmarks/mafft/pairlocalalign
with AA: 25.3016% +/- 17.8614%
without AA: 38.6629% +/- 14.9391%
(significantly in favor of AA)
MultiSource/Benchmarks/sim/sim
with AA: N/A
without AA: 13.4844% +/- 7.18195%
(significantly in favor of AA)
SingleSource/Benchmarks/BenchmarkGame/Large/fasta
with AA: 15.0664% +/- 6.70216%
without AA: 12.7747% +/- 8.43043%
SingleSource/Benchmarks/BenchmarkGame/puzzle
with AA: 82.2713% +/- 26.3567%
without AA: 75.7525% +/- 41.1842%
SingleSource/Benchmarks/Misc/flops-2
with AA: -37.1621% +/- 20.7964%
without AA: -35.2342% +/- 20.2999%
(significantly in favor of AA)
These are 99.5% confidence intervals from 5 runs per configuration. Regarding
the choice to turn on AA during CodeGen, of these results, four seem
significantly in favor of using AA, and one seems significantly against. I'm
not making this decision based on these numbers alone, but these results
seem consistent with results I have from other tests, and so I think that, on
balance, using AA is a win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195981 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-30 20:55:12 +00:00
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case PPC::DIR_PWR7:
|
2014-06-26 13:36:19 +00:00
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case PPC::DIR_PWR8:
|
2013-09-11 23:05:25 +00:00
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return true;
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}
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}
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bool PPCSubtarget::enableMachineScheduler() const {
|
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|
|
// Enable MI scheduling for the embedded cores.
|
|
|
|
// FIXME: Enable this for all cores (some additional modeling
|
|
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|
// may be necessary).
|
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|
return needsAggressiveScheduling(DarwinDirective);
|
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|
}
|
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|
2014-07-15 22:39:58 +00:00
|
|
|
// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
|
|
|
|
bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
|
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PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
|
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|
|
return TargetSubtargetInfo::ANTIDEP_ALL;
|
|
|
|
}
|
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|
|
|
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void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
|
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|
|
CriticalPathRCs.clear();
|
|
|
|
CriticalPathRCs.push_back(isPPC64() ?
|
|
|
|
&PPC::G8RCRegClass : &PPC::GPRCRegClass);
|
|
|
|
}
|
|
|
|
|
2013-09-11 23:05:25 +00:00
|
|
|
void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
|
|
|
|
MachineInstr *begin,
|
|
|
|
MachineInstr *end,
|
|
|
|
unsigned NumRegionInstrs) const {
|
|
|
|
if (needsAggressiveScheduling(DarwinDirective)) {
|
|
|
|
Policy.OnlyTopDown = false;
|
|
|
|
Policy.OnlyBottomUp = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Spilling is generally expensive on all PPC cores, so always enable
|
|
|
|
// register-pressure tracking.
|
|
|
|
Policy.ShouldTrackPressure = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool PPCSubtarget::useAA() const {
|
|
|
|
// Use AA during code generation for the embedded cores.
|
|
|
|
return needsAggressiveScheduling(DarwinDirective);
|
|
|
|
}
|
|
|
|
|