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154 lines
5.0 KiB
C
154 lines
5.0 KiB
C
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//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that NVPTX uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef NVPTXISELLOWERING_H
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#define NVPTXISELLOWERING_H
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#include "NVPTX.h"
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#include "NVPTXSubtarget.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace NVPTXISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Wrapper,
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CALL,
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RET_FLAG,
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LOAD_PARAM,
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NVBuiltin,
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DeclareParam,
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DeclareScalarParam,
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DeclareRetParam,
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DeclareRet,
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DeclareScalarRet,
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LoadParam,
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StoreParam,
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StoreParamS32, // to sext and store a <32bit value, not used currently
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StoreParamU32, // to zext and store a <32bit value, not used currently
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MoveToParam,
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PrintCall,
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PrintCallUni,
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CallArgBegin,
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CallArg,
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LastCallArg,
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CallArgEnd,
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CallVoid,
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CallVal,
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CallSymbol,
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Prototype,
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MoveParam,
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MoveRetval,
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MoveToRetval,
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StoreRetval,
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PseudoUseParam,
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RETURN,
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CallSeqBegin,
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CallSeqEnd,
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Dummy
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class NVPTXTargetLowering : public TargetLowering {
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public:
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explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
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SelectionDAG &DAG) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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bool isTypeSupportedInIntrinsic(MVT VT) const;
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bool getTgtMemIntrinsic(IntrinsicInfo& Info, const CallInst &I,
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unsigned Intrinsic) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type
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/// Used to guide target specific optimizations, like loop strength
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/// reduction (LoopStrengthReduce.cpp) and memory optimization for
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/// address mode (CodeGenPrepare.cpp)
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virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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virtual EVT getSetCCResultType(EVT VT) const {
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return MVT::i1;
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}
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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// This will be re-added once the necessary changes to LowerCallTo are
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// upstreamed.
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// virtual SDValue
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// LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
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// bool isVarArg, bool doesNotRet, bool &isTailCall,
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// const SmallVectorImpl<ISD::OutputArg> &Outs,
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// const SmallVectorImpl<SDValue> &OutVals,
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// const SmallVectorImpl<ISD::InputArg> &Ins,
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// DebugLoc dl, SelectionDAG &DAG,
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// SmallVectorImpl<SDValue> &InVals,
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// Type *retTy, const ArgListTy &Args) const;
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std::string getPrototype(Type *, const ArgListTy &,
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const SmallVectorImpl<ISD::OutputArg> &,
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unsigned retAlignment) const;
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virtual SDValue
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LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl,
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SelectionDAG &DAG) const;
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virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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NVPTXTargetMachine *nvTM;
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// PTX always uses 32-bit shift amounts
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virtual MVT getShiftAmountTy(EVT LHSTy) const {
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return MVT::i32;
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}
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private:
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const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
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SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx, EVT =
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MVT::i32) const;
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SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT = MVT::i32) const;
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SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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};
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} // namespace llvm
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#endif // NVPTXISELLOWERING_H
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