2011-04-15 21:51:11 +00:00
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//===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
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2007-07-11 22:44:21 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-07-11 22:44:21 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-07-11 22:44:21 +00:00
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//
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// This file declares the Mips specific subclass of MachineFunctionInfo.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-07-11 22:44:21 +00:00
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#ifndef MIPS_MACHINE_FUNCTION_INFO_H
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#define MIPS_MACHINE_FUNCTION_INFO_H
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2011-05-20 01:17:58 +00:00
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#include <utility>
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2009-01-05 17:59:02 +00:00
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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namespace llvm {
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/// MipsFunctionInfo - This class is derived from MachineFunction private
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/// Mips target-specific information for each MachineFunction.
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class MipsFunctionInfo : public MachineFunctionInfo {
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private:
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2011-06-21 00:40:49 +00:00
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MachineFunction& MF;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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/// SRetReturnReg - Some subtargets require that sret lowering includes
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/// returning the value of the returned struct in a register. This field
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/// holds the virtual register into which the sret argument is passed.
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unsigned SRetReturnReg;
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2009-06-03 20:30:14 +00:00
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/// GlobalBaseReg - keeps track of the virtual register initialized for
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/// use as the global base register. This is used for PIC in some PIC
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/// relocation models.
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unsigned GlobalBaseReg;
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2010-04-17 14:41:14 +00:00
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/// VarArgsFrameIndex - FrameIndex for start of varargs area.
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int VarArgsFrameIndex;
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2011-05-20 01:17:58 +00:00
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// Range of frame object indices.
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// InArgFIRange: Range of indices of all frame objects created during call to
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// LowerFormalArguments.
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// OutArgFIRange: Range of indices of all frame objects created during call to
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// LowerCall except for the frame object for restoring $gp.
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std::pair<int, int> InArgFIRange, OutArgFIRange;
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int GPFI; // Index of the frame object for restoring $gp
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mutable int DynAllocFI; // Frame index of dynamically allocated stack area.
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2011-05-25 17:52:48 +00:00
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unsigned MaxCallFrameSize;
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2011-05-31 02:54:07 +00:00
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2007-07-11 22:44:21 +00:00
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public:
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2010-09-28 10:06:53 +00:00
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MipsFunctionInfo(MachineFunction& MF)
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2011-06-21 00:40:49 +00:00
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: MF(MF), SRetReturnReg(0), GlobalBaseReg(0),
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2011-05-20 01:17:58 +00:00
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VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)),
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2011-06-21 00:40:49 +00:00
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OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0),
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MaxCallFrameSize(0)
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{}
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bool isInArgFI(int FI) const {
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return FI <= InArgFIRange.first && FI >= InArgFIRange.second;
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}
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void setLastInArgFI(int FI) { InArgFIRange.second = FI; }
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bool isOutArgFI(int FI) const {
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return FI <= OutArgFIRange.first && FI >= OutArgFIRange.second;
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}
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void extendOutArgFIRange(int FirstFI, int LastFI) {
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if (!OutArgFIRange.second)
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// this must be the first time this function was called.
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OutArgFIRange.first = FirstFI;
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OutArgFIRange.second = LastFI;
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}
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2011-05-23 20:16:59 +00:00
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int getGPFI() const { return GPFI; }
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void setGPFI(int FI) { GPFI = FI; }
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bool needGPSaveRestore() const { return getGPFI(); }
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2011-05-20 01:17:58 +00:00
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bool isGPFI(int FI) const { return GPFI && GPFI == FI; }
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2007-10-09 03:01:19 +00:00
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2011-06-21 00:40:49 +00:00
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// The first call to this function creates a frame object for dynamically
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// allocated stack area.
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int getDynAllocFI() const {
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if (!DynAllocFI)
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DynAllocFI = MF.getFrameInfo()->CreateFixedObject(4, 0, true);
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return DynAllocFI;
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}
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bool isDynAllocFI(int FI) const { return DynAllocFI && DynAllocFI == FI; }
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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unsigned getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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2009-06-03 20:30:14 +00:00
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unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
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void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
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2010-04-17 14:41:14 +00:00
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int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
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void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
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2011-05-20 01:17:58 +00:00
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2011-05-25 17:52:48 +00:00
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unsigned getMaxCallFrameSize() const { return MaxCallFrameSize; }
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void setMaxCallFrameSize(unsigned S) { MaxCallFrameSize = S; }
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2007-07-11 22:44:21 +00:00
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};
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} // end of namespace llvm
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2007-08-28 05:04:41 +00:00
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#endif // MIPS_MACHINE_FUNCTION_INFO_H
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