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llvm-6502/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

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Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:29:14 +00:00
//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
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///
/// \file
/// \brief This file is part of the XCore Disassembler.
///
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//===----------------------------------------------------------------------===//
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#include "XCore.h"
#include "XCoreRegisterInfo.h"
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
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#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
[Modules] Make Support/Debug.h modular. This requires it to not change behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 22:55:11 +00:00
#define DEBUG_TYPE "xcore-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
namespace {
Update comments to match recommended doxygen style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
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/// \brief A disassembler class for XCore.
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
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class XCoreDisassembler : public MCDisassembler {
public:
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8
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XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
MCDisassembler(STI, Ctx) {}
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
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Update comments to match recommended doxygen style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
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/// \brief See MCDisassembler.
Add override to overriden virtual methods, remove virtual keywords. No functionality change. Changes made by clang-tidy + some manual cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217028 91177308-0d34-0410-b5e6-96231b3b80d8
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DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
const MemoryObject &region, uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const override;
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
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};
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}
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-16 17:37:34 +00:00
static bool readInstruction16(const MemoryObject &region,
uint64_t address,
uint64_t &size,
uint16_t &insn) {
uint8_t Bytes[4];
// We want to read exactly 2 Bytes of data.
Remove the Copied parameter from MemoryObject::readBytes. There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
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if (region.readBytes(address, 2, Bytes) == -1) {
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size = 0;
return false;
}
// Encoded as a little-endian 16-bit word in the stream.
insn = (Bytes[0] << 0) | (Bytes[1] << 8);
return true;
}
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static bool readInstruction32(const MemoryObject &region,
uint64_t address,
uint64_t &size,
uint32_t &insn) {
uint8_t Bytes[4];
// We want to read exactly 4 Bytes of data.
Remove the Copied parameter from MemoryObject::readBytes. There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
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if (region.readBytes(address, 4, Bytes) == -1) {
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size = 0;
return false;
}
// Encoded as a little-endian 32-bit word in the stream.
insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
(Bytes[3] << 24);
return true;
}
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8
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const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
return *(RegInfo->getRegClass(RC).begin() + RegNo);
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}
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[XCore] The RRegs register class is a superset of GRRegs. At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
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static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
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static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
[XCore] Remove '-' from back branch asm syntax. Instead operands are treated as negative immediates where the sign bit is implicit in the instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
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static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
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static DecodeStatus Decode2RInstruction(MCInst &Inst,
Fix parameter name in prototypes in XCoreDisassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
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unsigned Insn,
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2012-12-17 12:29:31 +00:00
uint64_t Address,
const void *Decoder);
[XCore] Add missing 2r instructions. These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
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static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
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static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
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unsigned Insn,
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2012-12-17 12:29:31 +00:00
uint64_t Address,
const void *Decoder);
static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
Fix parameter name in prototypes in XCoreDisassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
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unsigned Insn,
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uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support for rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
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static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
static DecodeStatus Decode3RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[XCore] Add TSETR instruction. This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:32:41 +00:00
static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembler support for 2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:22:43 +00:00
static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support for l2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:51:15 +00:00
static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support for l6r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23 20:08:11 +00:00
static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support for l5r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
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static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings / disassembly support for l4r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 21:55:32 +00:00
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add instruction encodings and disassembly for 1r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
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#include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 11)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
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}
[XCore] The RRegs register class is a superset of GRRegs. At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04 19:57:46 +00:00
static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 15)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
Add instruction encodings / disassembly support for rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:50:04 +00:00
static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val > 11)
return MCDisassembler::Fail;
static unsigned Values[] = {
32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
};
Inst.addOperand(MCOperand::CreateImm(Values[Val]));
return MCDisassembler::Success;
}
[XCore] Remove '-' from back branch asm syntax. Instead operands are treated as negative immediates where the sign bit is implicit in the instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 13:20:22 +00:00
static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
return MCDisassembler::Success;
}
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
static DecodeStatus
Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
unsigned Combined = fieldFromInstruction(Insn, 6, 5);
if (Combined < 27)
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
return MCDisassembler::Fail;
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
if (fieldFromInstruction(Insn, 5, 1)) {
if (Combined == 31)
return MCDisassembler::Fail;
Combined += 5;
}
Combined -= 27;
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
unsigned Op1High = Combined % 3;
unsigned Op2High = Combined / 3;
Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
return MCDisassembler::Success;
}
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
static DecodeStatus
Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
unsigned &Op3) {
unsigned Combined = fieldFromInstruction(Insn, 6, 5);
if (Combined >= 27)
return MCDisassembler::Fail;
unsigned Op1High = Combined % 3;
unsigned Op2High = (Combined / 3) % 3;
unsigned Op3High = Combined / 9;
Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
return MCDisassembler::Success;
}
static DecodeStatus
Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a 3R instruction.
unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
switch (Opcode) {
Add instruction encodings / disassembler support for 2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:22:43 +00:00
case 0x0:
Inst.setOpcode(XCore::STW_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x1:
Inst.setOpcode(XCore::LDW_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
case 0x2:
Inst.setOpcode(XCore::ADD_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x3:
Inst.setOpcode(XCore::SUB_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x4:
Inst.setOpcode(XCore::SHL_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x5:
Inst.setOpcode(XCore::SHR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x6:
Inst.setOpcode(XCore::EQ_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x7:
Inst.setOpcode(XCore::AND_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x8:
Inst.setOpcode(XCore::OR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x9:
Inst.setOpcode(XCore::LDW_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x10:
Inst.setOpcode(XCore::LD16S_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x11:
Inst.setOpcode(XCore::LD8U_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
Add instruction encodings / disassembler support for 2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:22:43 +00:00
case 0x12:
Inst.setOpcode(XCore::ADD_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x13:
Inst.setOpcode(XCore::SUB_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x14:
Inst.setOpcode(XCore::SHL_2rus);
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x15:
Inst.setOpcode(XCore::SHR_2rus);
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x16:
Inst.setOpcode(XCore::EQ_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
[XCore] Add TSETR instruction. This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:32:41 +00:00
case 0x17:
Inst.setOpcode(XCore::TSETR_3r);
return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
case 0x18:
Inst.setOpcode(XCore::LSS_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x19:
Inst.setOpcode(XCore::LSU_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
static DecodeStatus
Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
return S;
}
[XCore] Add missing 2r instructions. These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:38:05 +00:00
static DecodeStatus
Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
static DecodeStatus
DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
return S;
}
static DecodeStatus
Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 12:29:31 +00:00
return S;
}
Add instruction encodings / disassembly support for rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:50:04 +00:00
static DecodeStatus
DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op2));
Add instruction encodings / disassembly support for rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:50:04 +00:00
return S;
}
static DecodeStatus
DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
Add instruction encodings / disassembly support for rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:50:04 +00:00
return S;
}
static DecodeStatus
DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
Add instruction encodings / disassembly support for rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 13:50:04 +00:00
return S;
}
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
static DecodeStatus
DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
Add instruction encodings / disassembly support for l2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:51:15 +00:00
// Try and decode as a L3R / L2RUS instruction.
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
fieldFromInstruction(Insn, 27, 5) << 4;
switch (Opcode) {
case 0x0c:
Use the correct format in the STW / SETPSC instruction names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 21:25:12 +00:00
Inst.setOpcode(XCore::STW_l3r);
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x1c:
Inst.setOpcode(XCore::XOR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x2c:
Inst.setOpcode(XCore::ASHR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x3c:
Inst.setOpcode(XCore::LDAWF_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x4c:
Inst.setOpcode(XCore::LDAWB_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x5c:
Inst.setOpcode(XCore::LDA16F_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x6c:
Inst.setOpcode(XCore::LDA16B_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x7c:
Inst.setOpcode(XCore::MUL_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x8c:
Inst.setOpcode(XCore::DIVS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x9c:
Inst.setOpcode(XCore::DIVU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x10c:
Inst.setOpcode(XCore::ST16_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x11c:
Inst.setOpcode(XCore::ST8_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
Add instruction encodings / disassembly support for l2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:51:15 +00:00
case 0x12c:
Inst.setOpcode(XCore::ASHR_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
[XCore] Add missing l2rus instructions. These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27 22:28:30 +00:00
case 0x12d:
Inst.setOpcode(XCore::OUTPW_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x12e:
Inst.setOpcode(XCore::INPW_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
Add instruction encodings / disassembly support for l2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:51:15 +00:00
case 0x13c:
Inst.setOpcode(XCore::LDAWF_l2rus);
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x14c:
Inst.setOpcode(XCore::LDAWB_l2rus);
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
case 0x15c:
Inst.setOpcode(XCore::CRC_l3r);
return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
case 0x18c:
Inst.setOpcode(XCore::REMS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x19c:
Inst.setOpcode(XCore::REMU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
static DecodeStatus
DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
Op1, Op2);
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
if (S != MCDisassembler::Success)
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
return S;
}
static DecodeStatus
DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
Op1, Op2);
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
if (S != MCDisassembler::Success)
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
return S;
}
Add instruction encodings / disassembly support 3r instructions. It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
static DecodeStatus
Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
[XCore] Add TSETR instruction. This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:32:41 +00:00
static DecodeStatus
Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
Inst.addOperand(MCOperand::CreateImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
Add instruction encodings / disassembler support for 2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:22:43 +00:00
static DecodeStatus
Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op3));
}
return S;
}
static DecodeStatus
Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeBitpOperand(Inst, Op3, Address, Decoder);
}
return S;
}
Add instruction encodings / disassembly support for l3r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:37:49 +00:00
static DecodeStatus
DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
static DecodeStatus
DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
Add instruction encodings / disassembly support for l2rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 18:51:15 +00:00
static DecodeStatus
DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op3));
}
return S;
}
static DecodeStatus
DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeBitpOperand(Inst, Op3, Address, Decoder);
}
return S;
}
Add instruction encodings / disassembly support for l6r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23 20:08:11 +00:00
static DecodeStatus
DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3, Op4, Op5, Op6;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S != MCDisassembler::Success)
return S;
S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
if (S != MCDisassembler::Success)
return S;
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
return S;
}
Add instruction encodings / disassembly support for l5r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 20:20:07 +00:00
static DecodeStatus
DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a L6R instruction.
Inst.clear();
unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
switch (Opcode) {
case 0x00:
Inst.setOpcode(XCore::LMUL_l6r);
return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
static DecodeStatus
DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3, Op4, Op5;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
return S;
}
Add instruction encodings / disassembly support for l4r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 21:55:32 +00:00
static DecodeStatus
DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
}
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
static DecodeStatus
DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
}
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:29:14 +00:00
MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
raw_ostream &vStream,
raw_ostream &cStream) const {
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
uint16_t insn16;
Add instruction encodings and disassembly for 1r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:37:34 +00:00
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
if (!readInstruction16(Region, Address, Size, insn16)) {
Add instruction encodings and disassembly for 1r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:37:34 +00:00
return Fail;
}
// Calling the auto-generated decoder function.
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
Address, this, STI);
Add instruction encodings and disassembly for 1r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:37:34 +00:00
if (Result != Fail) {
Size = 2;
return Result;
}
Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17 16:28:02 +00:00
uint32_t insn32;
if (!readInstruction32(Region, Address, Size, insn32)) {
return Fail;
}
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
if (Result != Fail) {
Size = 4;
return Result;
}
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:29:14 +00:00
return Fail;
}
namespace llvm {
extern Target TheXCoreTarget;
}
static MCDisassembler *createXCoreDisassembler(const Target &T,
[MC] Require an MCContext when constructing an MCDisassembler. This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 04:40:56 +00:00
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new XCoreDisassembler(STI, Ctx);
Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 17:29:14 +00:00
}
extern "C" void LLVMInitializeXCoreDisassembler() {
// Register the disassembler.
TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
createXCoreDisassembler);
}
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