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llvm-6502/test/MC/Disassembler/ARM/neon-tests.txt

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Specify cpu to unbreak tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 01:38:10 +00:00
# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
# CHECK: vbif q15, q7, q0
0x50 0xe1 0x7e 0xf3
# CHECK: vcvt.f32.s32 q15, q0, #1
0x50 0xee 0xff 0xf2
# CHECK: vdup.32 q3, d1[0]
0x41 0x6c 0xb4 0xf3
chase owen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:55:24 +00:00
# CHECK: vld1.8 {d17, d18}, [r6], r5
tweak this to pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:50:17 +00:00
0x05 0x1a 0x66 0xf4
ARM disassembler did not react to recent changes to the NEON instruction table. VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 16:20:34 +00:00
chase owen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:55:24 +00:00
# CHECK: vld1.8 {d17, d18, d19}, [r6], r5
Reapply r113875 with additional cleanups. "The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 23:54:06 +00:00
0x05 0x16 0x66 0xf4
chase owen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 23:55:24 +00:00
# CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
0x07 0x00 0x22 0xf4
# CHECK: vld4.8 {d4, d6, d8, d10}, [r2]
0x0f 0x41 0x22 0xf4
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22 10:01:33 +00:00
# CHECK: vld1.32 {d3[], d4[]}, [r0:32]!
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions (single element or n-element structure to all lanes). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 00:10:45 +00:00
0xbd 0x3c 0xa0 0xf4
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22 10:01:33 +00:00
# CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0:64]!
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions (single element or n-element structure to all lanes). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 00:10:45 +00:00
0x7d 0x3f 0xa0 0xf4
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 18:46:47 +00:00
# CHECK: vorr d0, d15, d15
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
0x1f 0x01 0x2f 0xf2
Simplify some uses of utohexstr. As a side effect hex is printed lowercase instead of uppercase now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 21:00:59 +00:00
# CHECK: vmov.i64 q6, #0xff00ff00ff
Minor change to make the test case comply with Vd<0> == '0' when Q == '1'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:48:31 +00:00
0x75 0xce 0x81 0xf2
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16 22:40:20 +00:00
Add support for disassembling VMVN (immediate) instructions. PR7747. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-31 05:57:44 +00:00
# CHECK: vmvn.i32 d0, #0x0
0x30 0x00 0x80 0xf2
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
# CHECK: vmul.f32 d0, d0, d6
0x16 0x0d 0x00 0xf3
# CHECK: vneg.f32 q0, q0
0xc0 0x07 0xb9 0xf3
# CHECK: vqrdmulh.s32 d0, d0, d3[1]
0x63 0x0d 0xa0 0xf2
# CHECK: vrshr.s32 d0, d0, #16
0x10 0x02 0xb0 0xf2
# CHECK: vshll.i16 q3, d1, #16
0x01 0x63 0xb6 0xf3
# CHECK: vsri.32 q15, q0, #1
0x50 0xe4 0xff 0xf3
# CHECK: vtbx.8 d18, {d4, d5, d6}, d7
0x47 0x2a 0xf4 0xf3
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:04:54 +00:00
# CHECK: vmov.f32 s0, #5.000000e-01
0x00 0x0a 0xb6 0xee
add a test of an edge case value for the FP immediate (needs all digits of precision) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:52:13 +00:00
# CHECK: vmov.f32 s0, #1.328125e-01
0x01 0x0a 0xb4 0xee
Fix vmov.f64 disassembly on targets where sizeof(long) != 8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:48:07 +00:00
# CHECK: vmov.f64 d0, #5.000000e-01
0x00 0x0b 0xb6 0xee
Add one more test case for VFP Load/Store Multiple (vpop). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:21:08 +00:00
# CHECK: vpop {d8}
0x02 0x8b 0xbd 0xec
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:40:38 +00:00
Simplify some uses of utohexstr. As a side effect hex is printed lowercase instead of uppercase now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 21:00:59 +00:00
# CHECK: vorr.i32 q15, #0x4f0000
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:40:38 +00:00
0x5f 0xe5 0xc4 0xf2
Handle the added VBICiv*i* NEON instructions, too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:04:39 +00:00
Simplify some uses of utohexstr. As a side effect hex is printed lowercase instead of uppercase now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 21:00:59 +00:00
# CHECK: vbic.i32 q2, #0xa900
A7.3 register encoding Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:57:07 +00:00
0x79 0x43 0x82 0xf3
Fix incorrect alignment for NEON VST2b32_UPD. rdar://problem/9225433 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 20:35:31 +00:00
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22 10:01:33 +00:00
# CHECK: vst2.32 {d16, d18}, [r2:64], r2
Fix incorrect alignment for NEON VST2b32_UPD. rdar://problem/9225433 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 20:35:31 +00:00
0x92 0x9 0x42 0xf4
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 18:27:46 +00:00
# CHECK: vmov.s8 r0, d8[1]
0x30 0x0b 0x58 0xee
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 20:49:02 +00:00
# CHECK: vmov r1, r0, d11
0x1b 0x1b 0x50 0xec
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values for USAD8 and USADA8. rdar://problem/9247060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 01:05:52 +00:00
# CHECK: usada8mi r8, r9, r5, r9
0x19 0x95 0x88 0x47
Add a VEXT test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 22:04:01 +00:00
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 20:55:18 +00:00
# CHECK: vext.32 q4, q2, q1, #1
Add a VEXT test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 22:04:01 +00:00
0x42 0x84 0xb4 0xf2
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