llvm-6502/test/CodeGen/X86/vshift_split.ll

; RUN: llc < %s -march=x86 -mattr=+sse2

; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
entry:
	%shr = lshr <2 x i64> %val, < i64 2, i64 3 >
	ret <2 x i64> %shr
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-08 23:54:48 +00:00			`; RUN: llc < %s -march=x86 -mattr=+sse2`
Fix getNode to allow a vector for the shift amount for shifts of vectors. Fix the shift amount when unrolling a vector shift into scalar shifts. Fix problem in getShuffleScalarElt where it assumes that the input of a bit convert must be a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60740 91177308-0d34-0410-b5e6-96231b3b80d8 2008-12-09 05:46:39 +00:00
			`; Example that requires splitting and expanding a vector shift.`
			`define <2 x i64> @update(<2 x i64> %val) nounwind readnone {`
			`entry:`
Make x86 test actually test x86 code generation. Fix the construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-22 03:13:10 +00:00			`%shr = lshr <2 x i64> %val, < i64 2, i64 3 >`
Fix getNode to allow a vector for the shift amount for shifts of vectors. Fix the shift amount when unrolling a vector shift into scalar shifts. Fix problem in getShuffleScalarElt where it assumes that the input of a bit convert must be a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60740 91177308-0d34-0410-b5e6-96231b3b80d8 2008-12-09 05:46:39 +00:00			`ret <2 x i64> %shr`
			`}`