2005-11-16 22:59:19 +00:00
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//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
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2005-11-16 01:54:32 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-11-16 01:54:32 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a DAG pattern matching instruction selector for X86,
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// converting from a legalized dag to a X86 dag.
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//
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//===----------------------------------------------------------------------===//
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2006-08-07 22:28:20 +00:00
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#define DEBUG_TYPE "x86-isel"
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2005-11-16 01:54:32 +00:00
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#include "X86.h"
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2006-01-11 06:09:51 +00:00
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#include "X86InstrBuilder.h"
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2006-03-13 23:20:37 +00:00
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#include "X86ISelLowering.h"
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2008-01-05 00:41:47 +00:00
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#include "X86MachineFunctionInfo.h"
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2006-01-11 01:15:34 +00:00
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#include "X86RegisterInfo.h"
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2005-11-16 01:54:32 +00:00
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#include "X86Subtarget.h"
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2006-03-13 23:20:37 +00:00
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#include "X86TargetMachine.h"
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2005-11-19 02:11:08 +00:00
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#include "llvm/GlobalValue.h"
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2006-01-11 01:15:34 +00:00
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#include "llvm/Instructions.h"
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2006-03-25 06:47:10 +00:00
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#include "llvm/Intrinsics.h"
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2006-01-11 01:15:34 +00:00
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#include "llvm/Support/CFG.h"
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2007-01-12 23:22:14 +00:00
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#include "llvm/Type.h"
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2005-11-19 02:11:08 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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2005-11-16 01:54:32 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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2006-01-10 20:26:56 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2006-01-11 01:15:34 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2005-11-16 01:54:32 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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2008-09-26 23:41:32 +00:00
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#include "llvm/Target/TargetOptions.h"
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2006-09-08 06:48:29 +00:00
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#include "llvm/Support/Debug.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2006-09-08 06:48:29 +00:00
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#include "llvm/Support/MathExtras.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/raw_ostream.h"
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2008-04-25 08:22:20 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2005-11-16 01:54:32 +00:00
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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2006-12-19 22:59:26 +00:00
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STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
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2005-11-16 01:54:32 +00:00
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//===----------------------------------------------------------------------===//
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// Pattern Matcher Implementation
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//===----------------------------------------------------------------------===//
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2005-11-19 02:11:08 +00:00
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namespace {
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/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
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2008-07-27 21:46:04 +00:00
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/// SDValue's instead of register numbers for the leaves of the matched
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2005-11-19 02:11:08 +00:00
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/// tree.
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struct X86ISelAddressMode {
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enum {
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RegBase,
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2006-05-24 17:04:05 +00:00
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FrameIndexBase
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2005-11-19 02:11:08 +00:00
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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2008-07-27 21:46:04 +00:00
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SDValue Reg;
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2005-11-19 02:11:08 +00:00
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int FrameIndex;
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} Base;
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unsigned Scale;
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2008-07-27 21:46:04 +00:00
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SDValue IndexReg;
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2008-11-11 15:52:29 +00:00
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int32_t Disp;
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2009-04-08 21:14:34 +00:00
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SDValue Segment;
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2005-11-19 02:11:08 +00:00
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GlobalValue *GV;
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2006-02-25 10:09:08 +00:00
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Constant *CP;
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2009-11-01 03:25:03 +00:00
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BlockAddress *BlockAddr;
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2006-09-08 06:48:29 +00:00
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const char *ES;
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int JT;
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2006-02-25 10:09:08 +00:00
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unsigned Align; // CP alignment.
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2009-06-26 05:51:45 +00:00
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unsigned char SymbolFlags; // X86II::MO_*
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2005-11-19 02:11:08 +00:00
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X86ISelAddressMode()
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Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
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2009-11-01 03:25:03 +00:00
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Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
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2009-08-25 17:47:44 +00:00
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SymbolFlags(X86II::MO_NO_FLAG) {
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2005-11-19 02:11:08 +00:00
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}
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2009-02-07 00:43:41 +00:00
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bool hasSymbolicDisplacement() const {
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2009-11-01 03:25:03 +00:00
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return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
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2009-02-07 00:43:41 +00:00
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}
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Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
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bool hasBaseOrIndexReg() const {
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return IndexReg.getNode() != 0 || Base.Reg.getNode() != 0;
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}
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/// isRIPRelative - Return true if this addressing mode is already RIP
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/// relative.
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bool isRIPRelative() const {
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if (BaseType != RegBase) return false;
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if (RegisterSDNode *RegNode =
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dyn_cast_or_null<RegisterSDNode>(Base.Reg.getNode()))
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return RegNode->getReg() == X86::RIP;
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return false;
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}
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void setBaseReg(SDValue Reg) {
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BaseType = RegBase;
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Base.Reg = Reg;
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}
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2009-02-07 00:43:41 +00:00
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2008-08-11 23:46:25 +00:00
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void dump() {
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2010-01-05 01:29:08 +00:00
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dbgs() << "X86ISelAddressMode " << this << '\n';
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dbgs() << "Base.Reg ";
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2009-08-07 21:33:25 +00:00
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if (Base.Reg.getNode() != 0)
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Base.Reg.getNode()->dump();
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else
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2010-01-05 01:29:08 +00:00
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dbgs() << "nul";
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dbgs() << " Base.FrameIndex " << Base.FrameIndex << '\n'
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2009-08-23 11:52:17 +00:00
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<< " Scale" << Scale << '\n'
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<< "IndexReg ";
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2009-08-07 21:33:25 +00:00
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if (IndexReg.getNode() != 0)
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IndexReg.getNode()->dump();
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else
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2010-01-05 01:29:08 +00:00
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dbgs() << "nul";
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dbgs() << " Disp " << Disp << '\n'
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2009-08-23 11:52:17 +00:00
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<< "GV ";
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2009-08-07 21:33:25 +00:00
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if (GV)
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GV->dump();
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else
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2010-01-05 01:29:08 +00:00
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dbgs() << "nul";
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dbgs() << " CP ";
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2009-08-07 21:33:25 +00:00
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if (CP)
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CP->dump();
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else
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2010-01-05 01:29:08 +00:00
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dbgs() << "nul";
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dbgs() << '\n'
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2009-08-23 11:52:17 +00:00
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<< "ES ";
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2009-08-07 21:33:25 +00:00
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if (ES)
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2010-01-05 01:29:08 +00:00
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dbgs() << ES;
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2009-08-07 21:33:25 +00:00
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else
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2010-01-05 01:29:08 +00:00
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dbgs() << "nul";
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dbgs() << " JT" << JT << " Align" << Align << '\n';
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2008-08-11 23:46:25 +00:00
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}
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2005-11-19 02:11:08 +00:00
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};
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}
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2005-11-16 01:54:32 +00:00
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namespace {
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2010-03-17 23:58:35 +00:00
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class X86ISelListener : public SelectionDAG::DAGUpdateListener {
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SmallSet<SDNode*, 4> Deletes;
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public:
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explicit X86ISelListener() {}
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virtual void NodeDeleted(SDNode *N, SDNode *E) {
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Deletes.insert(N);
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}
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virtual void NodeUpdated(SDNode *N) {
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// Ignore updates.
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}
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bool IsDeleted(SDNode *N) {
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return Deletes.count(N);
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}
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};
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2005-11-16 01:54:32 +00:00
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//===--------------------------------------------------------------------===//
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/// ISel - X86 specific code to select X86 machine instructions for
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/// SelectionDAG operations.
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///
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2009-10-25 06:33:48 +00:00
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class X86DAGToDAGISel : public SelectionDAGISel {
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2005-11-16 01:54:32 +00:00
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/// X86Lowering - This object fully describes how to lower LLVM code to an
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/// X86-specific SelectionDAG.
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2008-10-03 16:55:19 +00:00
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X86TargetLowering &X86Lowering;
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2005-11-16 01:54:32 +00:00
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
|
2006-02-18 00:15:05 +00:00
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2008-09-26 23:41:32 +00:00
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/// OptForSize - If true, selector should try to optimize for code size
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/// instead of performance.
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bool OptForSize;
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2005-11-16 01:54:32 +00:00
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public:
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2009-04-29 23:29:43 +00:00
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explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
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2009-04-29 00:15:41 +00:00
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: SelectionDAGISel(tm, OptLevel),
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2009-06-03 20:20:00 +00:00
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X86Lowering(*tm.getTargetLowering()),
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Subtarget(&tm.getSubtarget<X86Subtarget>()),
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2008-10-01 23:18:38 +00:00
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OptForSize(false) {}
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2005-11-16 01:54:32 +00:00
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virtual const char *getPassName() const {
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return "X86 DAG->DAG Instruction Selection";
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}
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2007-09-25 21:52:30 +00:00
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
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2010-02-15 19:41:07 +00:00
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virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
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2010-03-02 06:34:30 +00:00
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virtual void PreprocessISelDAG();
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2005-11-16 01:54:32 +00:00
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// Include the pieces autogenerated from the target description.
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#include "X86GenDAGISel.inc"
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private:
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2010-01-05 01:24:18 +00:00
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SDNode *Select(SDNode *N);
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2008-10-02 18:53:47 +00:00
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SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
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2009-08-10 22:56:29 +00:00
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SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
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2005-11-16 01:54:32 +00:00
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2009-04-08 21:14:34 +00:00
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bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
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bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
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2009-04-12 21:55:03 +00:00
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bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
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2009-07-22 23:26:55 +00:00
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bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
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bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
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2010-03-17 23:58:35 +00:00
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X86ISelListener &DeadNodes,
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2009-07-22 23:26:55 +00:00
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unsigned Depth);
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2009-03-31 16:16:57 +00:00
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bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
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2010-01-05 01:24:18 +00:00
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bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
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2009-04-08 21:14:34 +00:00
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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2010-01-05 01:24:18 +00:00
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bool SelectLEAAddr(SDNode *Op, SDValue N, SDValue &Base,
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2008-07-27 21:46:04 +00:00
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SDValue &Scale, SDValue &Index, SDValue &Disp);
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2010-01-05 01:24:18 +00:00
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bool SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
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2009-06-20 20:38:48 +00:00
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SDValue &Scale, SDValue &Index, SDValue &Disp);
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2010-03-01 22:51:11 +00:00
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bool SelectScalarSSELoad(SDNode *Root, SDValue N,
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2010-02-16 22:35:06 +00:00
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SDValue &Base, SDValue &Scale,
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2008-07-27 21:46:04 +00:00
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SDValue &Index, SDValue &Disp,
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2009-04-08 21:14:34 +00:00
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SDValue &Segment,
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2010-02-21 03:17:59 +00:00
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SDValue &NodeWithChain);
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2010-01-05 01:24:18 +00:00
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bool TryFoldLoad(SDNode *P, SDValue N,
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2008-07-27 21:46:04 +00:00
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SDValue &Base, SDValue &Scale,
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2009-04-08 21:14:34 +00:00
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SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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2010-03-02 06:34:30 +00:00
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2006-06-08 18:03:49 +00:00
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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2008-07-27 21:46:04 +00:00
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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2006-06-08 18:03:49 +00:00
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char ConstraintCode,
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2008-08-23 02:25:05 +00:00
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std::vector<SDValue> &OutOps);
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2006-06-08 18:03:49 +00:00
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2007-09-25 21:52:30 +00:00
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void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
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2008-07-27 21:46:04 +00:00
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inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
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|
|
SDValue &Scale, SDValue &Index,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Disp, SDValue &Segment) {
|
2005-12-12 21:49:40 +00:00
|
|
|
Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
|
2006-09-08 06:48:29 +00:00
|
|
|
CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
|
|
|
|
AM.Base.Reg;
|
2005-12-17 09:13:43 +00:00
|
|
|
Scale = getI8Imm(AM.Scale);
|
2005-12-12 21:49:40 +00:00
|
|
|
Index = AM.IndexReg;
|
2006-09-08 06:48:29 +00:00
|
|
|
// These are 32-bit even in 64-bit mode since RIP relative offset
|
|
|
|
// is 32-bit.
|
|
|
|
if (AM.GV)
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
|
2009-06-26 05:51:45 +00:00
|
|
|
AM.SymbolFlags);
|
2006-09-08 06:48:29 +00:00
|
|
|
else if (AM.CP)
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
|
2009-06-26 05:51:45 +00:00
|
|
|
AM.Align, AM.Disp, AM.SymbolFlags);
|
2006-09-08 06:48:29 +00:00
|
|
|
else if (AM.ES)
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
|
2006-09-08 06:48:29 +00:00
|
|
|
else if (AM.JT != -1)
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
|
2009-11-01 03:25:03 +00:00
|
|
|
else if (AM.BlockAddr)
|
2009-11-20 23:18:13 +00:00
|
|
|
Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
|
|
|
|
true, AM.SymbolFlags);
|
2006-09-08 06:48:29 +00:00
|
|
|
else
|
2009-08-11 20:47:22 +00:00
|
|
|
Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
|
2009-04-08 21:14:34 +00:00
|
|
|
|
|
|
|
if (AM.Segment.getNode())
|
|
|
|
Segment = AM.Segment;
|
|
|
|
else
|
2009-08-11 20:47:22 +00:00
|
|
|
Segment = CurDAG->getRegister(0, MVT::i32);
|
2005-12-12 21:49:40 +00:00
|
|
|
}
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
/// getI8Imm - Return a target constant with the specified value, of type
|
|
|
|
/// i8.
|
2008-07-27 21:46:04 +00:00
|
|
|
inline SDValue getI8Imm(unsigned Imm) {
|
2009-08-11 20:47:22 +00:00
|
|
|
return CurDAG->getTargetConstant(Imm, MVT::i8);
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
/// getI16Imm - Return a target constant with the specified value, of type
|
|
|
|
/// i16.
|
2008-07-27 21:46:04 +00:00
|
|
|
inline SDValue getI16Imm(unsigned Imm) {
|
2009-08-11 20:47:22 +00:00
|
|
|
return CurDAG->getTargetConstant(Imm, MVT::i16);
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// getI32Imm - Return a target constant with the specified value, of type
|
|
|
|
/// i32.
|
2008-07-27 21:46:04 +00:00
|
|
|
inline SDValue getI32Imm(unsigned Imm) {
|
2009-08-11 20:47:22 +00:00
|
|
|
return CurDAG->getTargetConstant(Imm, MVT::i32);
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
2006-02-10 22:24:32 +00:00
|
|
|
|
2008-09-23 18:22:58 +00:00
|
|
|
/// getGlobalBaseReg - Return an SDNode that returns the value of
|
|
|
|
/// the global base register. Output instructions required to
|
|
|
|
/// initialize the global base register, if necessary.
|
|
|
|
///
|
2006-08-26 05:34:46 +00:00
|
|
|
SDNode *getGlobalBaseReg();
|
2006-02-18 00:15:05 +00:00
|
|
|
|
2009-06-03 20:20:00 +00:00
|
|
|
/// getTargetMachine - Return a reference to the TargetMachine, casted
|
|
|
|
/// to the target-specific type.
|
|
|
|
const X86TargetMachine &getTargetMachine() {
|
|
|
|
return static_cast<const X86TargetMachine &>(TM);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
|
|
|
|
/// to the target-specific type.
|
|
|
|
const X86InstrInfo *getInstrInfo() {
|
|
|
|
return getTargetMachine().getInstrInfo();
|
|
|
|
}
|
2005-11-16 01:54:32 +00:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2006-08-08 00:31:00 +00:00
|
|
|
|
2010-02-15 19:41:07 +00:00
|
|
|
bool
|
|
|
|
X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
|
2009-04-29 23:29:43 +00:00
|
|
|
if (OptLevel == CodeGenOpt::None) return false;
|
2006-10-14 08:33:25 +00:00
|
|
|
|
2010-02-15 19:41:07 +00:00
|
|
|
if (!N.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (N.getOpcode() != ISD::LOAD)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If N is a load, do additional profitability checks.
|
|
|
|
if (U == Root) {
|
2008-11-27 00:49:46 +00:00
|
|
|
switch (U->getOpcode()) {
|
|
|
|
default: break;
|
2010-01-04 20:51:50 +00:00
|
|
|
case X86ISD::ADD:
|
|
|
|
case X86ISD::SUB:
|
|
|
|
case X86ISD::AND:
|
|
|
|
case X86ISD::XOR:
|
|
|
|
case X86ISD::OR:
|
2008-11-27 00:49:46 +00:00
|
|
|
case ISD::ADD:
|
|
|
|
case ISD::ADDC:
|
|
|
|
case ISD::ADDE:
|
|
|
|
case ISD::AND:
|
|
|
|
case ISD::OR:
|
|
|
|
case ISD::XOR: {
|
2009-04-10 10:09:34 +00:00
|
|
|
SDValue Op1 = U->getOperand(1);
|
|
|
|
|
2008-11-27 00:49:46 +00:00
|
|
|
// If the other operand is a 8-bit immediate we should fold the immediate
|
|
|
|
// instead. This reduces code size.
|
|
|
|
// e.g.
|
|
|
|
// movl 4(%esp), %eax
|
|
|
|
// addl $4, %eax
|
|
|
|
// vs.
|
|
|
|
// movl $4, %eax
|
|
|
|
// addl 4(%esp), %eax
|
|
|
|
// The former is 2 bytes shorter. In case where the increment is 1, then
|
|
|
|
// the saving can be 4 bytes (by using incl %eax).
|
2009-04-10 10:09:34 +00:00
|
|
|
if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
|
2009-03-14 02:07:16 +00:00
|
|
|
if (Imm->getAPIntValue().isSignedIntN(8))
|
|
|
|
return false;
|
2009-04-10 10:09:34 +00:00
|
|
|
|
|
|
|
// If the other operand is a TLS address, we should fold it instead.
|
|
|
|
// This produces
|
|
|
|
// movl %gs:0, %eax
|
|
|
|
// leal i@NTPOFF(%eax), %eax
|
|
|
|
// instead of
|
|
|
|
// movl $i@NTPOFF, %eax
|
|
|
|
// addl %gs:0, %eax
|
|
|
|
// if the block also has an access to a second TLS address this will save
|
|
|
|
// a load.
|
|
|
|
// FIXME: This is probably also true for non TLS addresses.
|
|
|
|
if (Op1.getOpcode() == X86ISD::Wrapper) {
|
|
|
|
SDValue Val = Op1.getOperand(0);
|
|
|
|
if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
|
|
|
|
return false;
|
|
|
|
}
|
2008-11-27 00:49:46 +00:00
|
|
|
}
|
|
|
|
}
|
2010-02-15 19:41:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-03-14 03:48:46 +00:00
|
|
|
/// MoveBelowCallOrigChain - Replace the original chain operand of the call with
|
|
|
|
/// load's chain operand and move load below the call's chain operand.
|
|
|
|
static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
|
|
|
|
SDValue Call, SDValue OrigChain) {
|
2008-08-25 21:27:18 +00:00
|
|
|
SmallVector<SDValue, 8> Ops;
|
2010-03-14 03:48:46 +00:00
|
|
|
SDValue Chain = OrigChain.getOperand(0);
|
2009-01-26 18:43:34 +00:00
|
|
|
if (Chain.getNode() == Load.getNode())
|
|
|
|
Ops.push_back(Load.getOperand(0));
|
|
|
|
else {
|
|
|
|
assert(Chain.getOpcode() == ISD::TokenFactor &&
|
2010-03-14 03:48:46 +00:00
|
|
|
"Unexpected chain operand");
|
2009-01-26 18:43:34 +00:00
|
|
|
for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
|
|
|
|
if (Chain.getOperand(i).getNode() == Load.getNode())
|
|
|
|
Ops.push_back(Load.getOperand(0));
|
|
|
|
else
|
|
|
|
Ops.push_back(Chain.getOperand(i));
|
|
|
|
SDValue NewChain =
|
2009-02-06 01:31:28 +00:00
|
|
|
CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
|
2009-08-11 20:47:22 +00:00
|
|
|
MVT::Other, &Ops[0], Ops.size());
|
2009-01-26 18:43:34 +00:00
|
|
|
Ops.clear();
|
|
|
|
Ops.push_back(NewChain);
|
|
|
|
}
|
2010-03-14 03:48:46 +00:00
|
|
|
for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
|
|
|
|
Ops.push_back(OrigChain.getOperand(i));
|
|
|
|
CurDAG->UpdateNodeOperands(OrigChain, &Ops[0], Ops.size());
|
2008-08-25 21:27:18 +00:00
|
|
|
CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
|
|
|
|
Load.getOperand(1), Load.getOperand(2));
|
|
|
|
Ops.clear();
|
2008-08-28 21:40:38 +00:00
|
|
|
Ops.push_back(SDValue(Load.getNode(), 1));
|
|
|
|
for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
|
2008-08-25 21:27:18 +00:00
|
|
|
Ops.push_back(Call.getOperand(i));
|
|
|
|
CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
|
|
|
|
}
|
|
|
|
|
|
|
|
/// isCalleeLoad - Return true if call address is a load and it can be
|
|
|
|
/// moved below CALLSEQ_START and the chains leading up to the call.
|
|
|
|
/// Return the CALLSEQ_START by reference as a second output.
|
2010-03-14 03:48:46 +00:00
|
|
|
/// In the case of a tail call, there isn't a callseq node between the call
|
|
|
|
/// chain and the load.
|
|
|
|
static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
|
2008-08-28 21:40:38 +00:00
|
|
|
if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
|
2008-08-25 21:27:18 +00:00
|
|
|
return false;
|
2008-08-28 21:40:38 +00:00
|
|
|
LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
|
2008-08-25 21:27:18 +00:00
|
|
|
if (!LD ||
|
|
|
|
LD->isVolatile() ||
|
|
|
|
LD->getAddressingMode() != ISD::UNINDEXED ||
|
|
|
|
LD->getExtensionType() != ISD::NON_EXTLOAD)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Now let's find the callseq_start.
|
2010-03-14 03:48:46 +00:00
|
|
|
while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
|
2008-08-25 21:27:18 +00:00
|
|
|
if (!Chain.hasOneUse())
|
|
|
|
return false;
|
|
|
|
Chain = Chain.getOperand(0);
|
|
|
|
}
|
2010-03-14 03:48:46 +00:00
|
|
|
|
|
|
|
if (!Chain.getNumOperands())
|
|
|
|
return false;
|
2009-01-26 18:43:34 +00:00
|
|
|
if (Chain.getOperand(0).getNode() == Callee.getNode())
|
|
|
|
return true;
|
|
|
|
if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
|
2009-09-15 01:22:01 +00:00
|
|
|
Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
|
|
|
|
Callee.getValue(1).hasOneUse())
|
2009-01-26 18:43:34 +00:00
|
|
|
return true;
|
|
|
|
return false;
|
2008-08-25 21:27:18 +00:00
|
|
|
}
|
|
|
|
|
2010-03-02 23:12:51 +00:00
|
|
|
void X86DAGToDAGISel::PreprocessISelDAG() {
|
2010-03-04 01:43:43 +00:00
|
|
|
// OptForSize is used in pattern predicates that isel is matching.
|
2010-03-02 23:12:51 +00:00
|
|
|
OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
|
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
|
|
|
|
E = CurDAG->allnodes_end(); I != E; ) {
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
|
2010-03-02 23:12:51 +00:00
|
|
|
|
2010-03-14 03:48:46 +00:00
|
|
|
if (OptLevel != CodeGenOpt::None &&
|
|
|
|
(N->getOpcode() == X86ISD::CALL ||
|
|
|
|
N->getOpcode() == X86ISD::TC_RETURN)) {
|
2010-03-02 23:12:51 +00:00
|
|
|
/// Also try moving call address load from outside callseq_start to just
|
|
|
|
/// before the call to allow it to be folded.
|
|
|
|
///
|
|
|
|
/// [Load chain]
|
|
|
|
/// ^
|
|
|
|
/// |
|
|
|
|
/// [Load]
|
|
|
|
/// ^ ^
|
|
|
|
/// | |
|
|
|
|
/// / \--
|
|
|
|
/// / |
|
|
|
|
///[CALLSEQ_START] |
|
|
|
|
/// ^ |
|
|
|
|
/// | |
|
|
|
|
/// [LOAD/C2Reg] |
|
|
|
|
/// | |
|
|
|
|
/// \ /
|
|
|
|
/// \ /
|
|
|
|
/// [CALL]
|
2010-03-14 03:48:46 +00:00
|
|
|
bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
|
2010-03-02 23:12:51 +00:00
|
|
|
SDValue Chain = N->getOperand(0);
|
|
|
|
SDValue Load = N->getOperand(1);
|
2010-03-14 03:48:46 +00:00
|
|
|
if (!isCalleeLoad(Load, Chain, HasCallSeq))
|
2010-03-02 23:12:51 +00:00
|
|
|
continue;
|
2010-03-14 03:48:46 +00:00
|
|
|
MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
|
2010-03-02 23:12:51 +00:00
|
|
|
++NumLoadMoved;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Lower fpround and fpextend nodes that target the FP stack to be store and
|
|
|
|
// load to the stack. This is a gross hack. We would like to simply mark
|
|
|
|
// these as being illegal, but when we do that, legalize produces these when
|
|
|
|
// it expands calls, then expands these in the same legalize pass. We would
|
|
|
|
// like dag combine to be able to hack on these between the call expansion
|
|
|
|
// and the node legalization. As such this pass basically does "really
|
|
|
|
// late" legalization of these inline with the X86 isel pass.
|
|
|
|
// FIXME: This should only happen when not compiled with -O0.
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// If the source and destination are SSE registers, then this is a legal
|
|
|
|
// conversion that should not be lowered.
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT SrcVT = N->getOperand(0).getValueType();
|
|
|
|
EVT DstVT = N->getValueType(0);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
|
|
|
|
bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
|
|
|
|
if (SrcIsSSE && DstIsSSE)
|
|
|
|
continue;
|
|
|
|
|
2008-03-09 07:05:32 +00:00
|
|
|
if (!SrcIsSSE && !DstIsSSE) {
|
|
|
|
// If this is an FPStack extension, it is a noop.
|
|
|
|
if (N->getOpcode() == ISD::FP_EXTEND)
|
|
|
|
continue;
|
|
|
|
// If this is a value-preserving FPStack truncation, it is a noop.
|
|
|
|
if (N->getConstantOperandVal(1))
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
// Here we could have an FP stack truncation or an FPStack <-> SSE convert.
|
|
|
|
// FPStack has extload and truncstore. SSE can fold direct loads into other
|
|
|
|
// operations. Based on this, decide what we want to do.
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT MemVT;
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
if (N->getOpcode() == ISD::FP_ROUND)
|
|
|
|
MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
|
|
|
|
else
|
|
|
|
MemVT = SrcIsSSE ? SrcVT : DstVT;
|
|
|
|
|
2008-08-23 02:25:05 +00:00
|
|
|
SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
|
2009-02-03 21:48:12 +00:00
|
|
|
DebugLoc dl = N->getDebugLoc();
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
|
|
|
|
// FIXME: optimize the case where the src/dest is a load or store?
|
2009-02-03 21:48:12 +00:00
|
|
|
SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
|
2008-08-23 02:25:05 +00:00
|
|
|
N->getOperand(0),
|
2010-02-15 16:57:43 +00:00
|
|
|
MemTmp, NULL, 0, MemVT,
|
|
|
|
false, false, 0);
|
2009-02-03 21:48:12 +00:00
|
|
|
SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
|
2010-02-15 16:57:43 +00:00
|
|
|
NULL, 0, MemVT, false, false, 0);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
|
|
|
|
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
|
|
|
|
// extload we created. This will cause general havok on the dag because
|
|
|
|
// anything below the conversion could be folded into other existing nodes.
|
|
|
|
// To avoid invalidating 'I', back it up to the convert node.
|
|
|
|
--I;
|
2008-08-23 02:25:05 +00:00
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
|
|
|
|
// Now that we did that, the node is dead. Increment the iterator to the
|
|
|
|
// next node to process, then delete N.
|
|
|
|
++I;
|
2008-08-23 02:25:05 +00:00
|
|
|
CurDAG->DeleteNode(N);
|
Significantly simplify and improve handling of FP function results on x86-32.
This case returns the value in ST(0) and then has to convert it to an SSE
register. This causes significant codegen ugliness in some cases. For
example in the trivial fp-stack-direct-ret.ll testcase we used to generate:
_bar:
subl $28, %esp
call L_foo$stub
fstpl 16(%esp)
movsd 16(%esp), %xmm0
movsd %xmm0, 8(%esp)
fldl 8(%esp)
addl $28, %esp
ret
because we move the result of foo() into an XMM register, then have to
move it back for the return of bar.
Instead of hacking ever-more special cases into the call result lowering code
we take a much simpler approach: on x86-32, fp return is modeled as always
returning into an f80 register which is then truncated to f32 or f64 as needed.
Similarly for a result, we model it as an extension to f80 + return.
This exposes the truncate and extensions to the dag combiner, allowing target
independent code to hack on them, eliminating them in this case. This gives
us this code for the example above:
_bar:
subl $12, %esp
call L_foo$stub
addl $12, %esp
ret
The nasty aspect of this is that these conversions are not legal, but we want
the second pass of dag combiner (post-legalize) to be able to hack on them.
To handle this, we lie to legalize and say they are legal, then custom expand
them on entry to the isel pass (PreprocessForFPConvert). This is gross, but
less gross than the code it is replacing :)
This also allows us to generate better code in several other cases. For
example on fp-stack-ret-conv.ll, we now generate:
_test:
subl $12, %esp
call L_foo$stub
fstps 8(%esp)
movl 16(%esp), %eax
cvtss2sd 8(%esp), %xmm0
movsd %xmm0, (%eax)
addl $12, %esp
ret
where before we produced (incidentally, the old bad code is identical to what
gcc produces):
_test:
subl $12, %esp
call L_foo$stub
fstpl (%esp)
cvtsd2ss (%esp), %xmm0
cvtss2sd %xmm0, %xmm0
movl 16(%esp), %eax
movsd %xmm0, (%eax)
addl $12, %esp
ret
Note that we generate slightly worse code on pr1505b.ll due to a scheduling
deficiency that is unrelated to this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46307 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-24 08:07:48 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
|
2007-09-25 21:52:30 +00:00
|
|
|
/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
|
|
|
|
/// the main function.
|
|
|
|
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
|
|
|
|
MachineFrameInfo *MFI) {
|
|
|
|
const TargetInstrInfo *TII = TM.getInstrInfo();
|
|
|
|
if (Subtarget->isTargetCygMing())
|
2010-04-02 20:16:16 +00:00
|
|
|
BuildMI(BB, DebugLoc(),
|
2009-02-13 02:33:27 +00:00
|
|
|
TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
|
2007-09-25 21:52:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
|
|
|
|
// If this is main, emit special code for main.
|
|
|
|
MachineBasicBlock *BB = MF.begin();
|
|
|
|
if (Fn.hasExternalLinkage() && Fn.getName() == "main")
|
|
|
|
EmitSpecialCodeForMain(BB, MF.getFrameInfo());
|
|
|
|
}
|
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
|
|
|
|
bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
|
|
|
|
X86ISelAddressMode &AM) {
|
|
|
|
assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
|
|
|
|
SDValue Segment = N.getOperand(0);
|
|
|
|
|
|
|
|
if (AM.Segment.getNode() == 0) {
|
|
|
|
AM.Segment = Segment;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
|
|
|
|
// This optimization is valid because the GNU TLS model defines that
|
|
|
|
// gs:0 (or fs:0 on X86-64) contains its own address.
|
|
|
|
// For more information see http://people.redhat.com/drepper/tls.pdf
|
|
|
|
|
|
|
|
SDValue Address = N.getOperand(1);
|
|
|
|
if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
|
|
|
|
!MatchSegmentBaseAddress (Address, AM))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
/// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
|
|
|
|
/// into an addressing mode. These wrap things that will resolve down into a
|
|
|
|
/// symbol reference. If no match is possible, this returns true, otherwise it
|
2009-08-05 23:01:26 +00:00
|
|
|
/// returns false.
|
2009-04-12 21:55:03 +00:00
|
|
|
bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// If the addressing mode already has a symbol as the displacement, we can
|
|
|
|
// never match another symbol.
|
2009-04-12 21:55:03 +00:00
|
|
|
if (AM.hasSymbolicDisplacement())
|
|
|
|
return true;
|
|
|
|
|
|
|
|
SDValue N0 = N.getOperand(0);
|
2009-08-05 23:01:26 +00:00
|
|
|
CodeModel::Model M = TM.getCodeModel();
|
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// Handle X86-64 rip-relative addresses. We check this before checking direct
|
|
|
|
// folding because RIP is preferable to non-RIP accesses.
|
|
|
|
if (Subtarget->is64Bit() &&
|
|
|
|
// Under X86-64 non-small code model, GV (and friends) are 64-bits, so
|
|
|
|
// they cannot be folded into immediate fields.
|
|
|
|
// FIXME: This can be improved for kernel and other models?
|
2009-08-21 15:41:56 +00:00
|
|
|
(M == CodeModel::Small || M == CodeModel::Kernel) &&
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// Base and index reg must be 0 in order to use %rip as base and lowering
|
|
|
|
// must allow RIP.
|
|
|
|
!AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
|
|
|
|
int64_t Offset = AM.Disp + G->getOffset();
|
2009-08-05 23:01:26 +00:00
|
|
|
if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.GV = G->getGlobal();
|
|
|
|
AM.Disp = Offset;
|
2009-06-26 05:51:45 +00:00
|
|
|
AM.SymbolFlags = G->getTargetFlags();
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
|
|
|
|
int64_t Offset = AM.Disp + CP->getOffset();
|
2009-08-05 23:01:26 +00:00
|
|
|
if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
|
2009-04-12 21:55:03 +00:00
|
|
|
AM.CP = CP->getConstVal();
|
|
|
|
AM.Align = CP->getAlignment();
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.Disp = Offset;
|
2009-06-26 05:56:49 +00:00
|
|
|
AM.SymbolFlags = CP->getTargetFlags();
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
|
|
|
|
AM.ES = S->getSymbol();
|
|
|
|
AM.SymbolFlags = S->getTargetFlags();
|
2009-11-01 03:25:03 +00:00
|
|
|
} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.JT = J->getIndex();
|
|
|
|
AM.SymbolFlags = J->getTargetFlags();
|
2009-11-01 03:25:03 +00:00
|
|
|
} else {
|
|
|
|
AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
|
2009-11-20 23:18:13 +00:00
|
|
|
AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
|
2009-04-12 21:55:03 +00:00
|
|
|
}
|
2009-08-05 23:01:26 +00:00
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (N.getOpcode() == X86ISD::WrapperRIP)
|
2009-08-11 20:47:22 +00:00
|
|
|
AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
|
2009-04-12 21:55:03 +00:00
|
|
|
return false;
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Handle the case when globals fit in our immediate field: This is true for
|
|
|
|
// X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
|
|
|
|
// mode, this results in a non-RIP-relative computation.
|
|
|
|
if (!Subtarget->is64Bit() ||
|
2009-08-05 23:01:26 +00:00
|
|
|
((M == CodeModel::Small || M == CodeModel::Kernel) &&
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
TM.getRelocationModel() == Reloc::Static)) {
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
|
|
|
|
AM.GV = G->getGlobal();
|
|
|
|
AM.Disp += G->getOffset();
|
|
|
|
AM.SymbolFlags = G->getTargetFlags();
|
|
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
|
|
|
|
AM.CP = CP->getConstVal();
|
|
|
|
AM.Align = CP->getAlignment();
|
|
|
|
AM.Disp += CP->getOffset();
|
|
|
|
AM.SymbolFlags = CP->getTargetFlags();
|
|
|
|
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
|
|
|
|
AM.ES = S->getSymbol();
|
|
|
|
AM.SymbolFlags = S->getTargetFlags();
|
2009-11-01 03:25:03 +00:00
|
|
|
} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.JT = J->getIndex();
|
|
|
|
AM.SymbolFlags = J->getTargetFlags();
|
2009-11-01 03:25:03 +00:00
|
|
|
} else {
|
|
|
|
AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
|
2009-11-20 23:18:13 +00:00
|
|
|
AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
}
|
2009-04-12 21:55:03 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
/// MatchAddress - Add the specified node to the specified addressing mode,
|
|
|
|
/// returning true if it cannot be done. This just pattern matches for the
|
2007-12-08 07:22:58 +00:00
|
|
|
/// addressing mode.
|
2009-07-22 23:26:55 +00:00
|
|
|
bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
|
2010-03-17 23:58:35 +00:00
|
|
|
X86ISelListener DeadNodes;
|
|
|
|
if (MatchAddressRecursively(N, AM, DeadNodes, 0))
|
2009-07-22 23:26:55 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
// Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
|
|
|
|
// a smaller encoding and avoids a scaled-index.
|
|
|
|
if (AM.Scale == 2 &&
|
|
|
|
AM.BaseType == X86ISelAddressMode::RegBase &&
|
|
|
|
AM.Base.Reg.getNode() == 0) {
|
|
|
|
AM.Base.Reg = AM.IndexReg;
|
|
|
|
AM.Scale = 1;
|
|
|
|
}
|
|
|
|
|
2009-08-20 18:23:44 +00:00
|
|
|
// Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
|
|
|
|
// because it has a smaller encoding.
|
|
|
|
// TODO: Which other code models can use this?
|
|
|
|
if (TM.getCodeModel() == CodeModel::Small &&
|
|
|
|
Subtarget->is64Bit() &&
|
|
|
|
AM.Scale == 1 &&
|
|
|
|
AM.BaseType == X86ISelAddressMode::RegBase &&
|
|
|
|
AM.Base.Reg.getNode() == 0 &&
|
|
|
|
AM.IndexReg.getNode() == 0 &&
|
2009-08-25 17:47:44 +00:00
|
|
|
AM.SymbolFlags == X86II::MO_NO_FLAG &&
|
2009-08-20 18:23:44 +00:00
|
|
|
AM.hasSymbolicDisplacement())
|
|
|
|
AM.Base.Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
|
|
|
|
|
2009-07-22 23:26:55 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
|
2010-03-17 23:58:35 +00:00
|
|
|
X86ISelListener &DeadNodes,
|
2009-07-22 23:26:55 +00:00
|
|
|
unsigned Depth) {
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
|
|
|
bool is64Bit = Subtarget->is64Bit();
|
2009-02-07 19:59:05 +00:00
|
|
|
DebugLoc dl = N.getDebugLoc();
|
2009-08-07 21:33:25 +00:00
|
|
|
DEBUG({
|
2010-01-05 01:29:08 +00:00
|
|
|
dbgs() << "MatchAddress: ";
|
2009-08-07 21:33:25 +00:00
|
|
|
AM.dump();
|
|
|
|
});
|
2007-08-13 20:03:06 +00:00
|
|
|
// Limit recursion.
|
|
|
|
if (Depth > 5)
|
2009-03-31 16:16:57 +00:00
|
|
|
return MatchAddressBase(N, AM);
|
2009-08-05 23:01:26 +00:00
|
|
|
|
|
|
|
CodeModel::Model M = TM.getCodeModel();
|
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
// If this is already a %rip relative address, we can only merge immediates
|
|
|
|
// into it. Instead of handling this in every case, we handle it here.
|
2006-09-08 06:48:29 +00:00
|
|
|
// RIP relative addressing: %rip + 32-bit displacement!
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.isRIPRelative()) {
|
|
|
|
// FIXME: JumpTable and ExternalSymbol address currently don't like
|
|
|
|
// displacements. It isn't very important, but this should be fixed for
|
|
|
|
// consistency.
|
|
|
|
if (!AM.ES && AM.JT != -1) return true;
|
2009-08-05 23:01:26 +00:00
|
|
|
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
|
|
|
|
int64_t Val = AM.Disp + Cst->getSExtValue();
|
2009-08-05 23:01:26 +00:00
|
|
|
if (X86::isOffsetSuitableForCodeModel(Val, M,
|
|
|
|
AM.hasSymbolicDisplacement())) {
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.Disp = Val;
|
2006-09-08 06:48:29 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
switch (N.getOpcode()) {
|
|
|
|
default: break;
|
2006-09-08 06:48:29 +00:00
|
|
|
case ISD::Constant: {
|
2008-11-11 15:52:29 +00:00
|
|
|
uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
|
2009-08-05 23:01:26 +00:00
|
|
|
if (!is64Bit ||
|
|
|
|
X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
|
|
|
|
AM.hasSymbolicDisplacement())) {
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.Disp += Val;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
case X86ISD::SegmentBaseAddress:
|
|
|
|
if (!MatchSegmentBaseAddress(N, AM))
|
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
|
2009-04-12 21:55:03 +00:00
|
|
|
case X86ISD::Wrapper:
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
case X86ISD::WrapperRIP:
|
2009-04-12 21:55:03 +00:00
|
|
|
if (!MatchWrapper(N, AM))
|
|
|
|
return false;
|
2005-12-08 02:01:35 +00:00
|
|
|
break;
|
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
case ISD::LOAD:
|
|
|
|
if (!MatchLoad(N, AM))
|
|
|
|
return false;
|
|
|
|
break;
|
|
|
|
|
2006-02-25 10:09:08 +00:00
|
|
|
case ISD::FrameIndex:
|
2008-08-31 15:37:04 +00:00
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase
|
|
|
|
&& AM.Base.Reg.getNode() == 0) {
|
2006-02-25 10:09:08 +00:00
|
|
|
AM.BaseType = X86ISelAddressMode::FrameIndexBase;
|
|
|
|
AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
|
2005-12-17 09:13:43 +00:00
|
|
|
return false;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
break;
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2005-11-19 02:11:08 +00:00
|
|
|
case ISD::SHL:
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
|
2007-12-08 07:22:58 +00:00
|
|
|
break;
|
|
|
|
|
2008-08-31 15:37:04 +00:00
|
|
|
if (ConstantSDNode
|
|
|
|
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
|
2008-09-12 16:56:44 +00:00
|
|
|
unsigned Val = CN->getZExtValue();
|
2009-07-22 23:26:55 +00:00
|
|
|
// Note that we handle x<<1 as (,x,2) rather than (x,x) here so
|
|
|
|
// that the base operand remains free for further matching. If
|
|
|
|
// the base doesn't end up getting used, a post-processing step
|
|
|
|
// in MatchAddress turns (,x,2) into (x,x), which is cheaper.
|
2007-12-08 07:22:58 +00:00
|
|
|
if (Val == 1 || Val == 2 || Val == 3) {
|
|
|
|
AM.Scale = 1 << Val;
|
2008-08-28 21:40:38 +00:00
|
|
|
SDValue ShVal = N.getNode()->getOperand(0);
|
2007-12-08 07:22:58 +00:00
|
|
|
|
|
|
|
// Okay, we know that we have a scale by now. However, if the scaled
|
|
|
|
// value is an add of something and a constant, we can fold the
|
|
|
|
// constant into the disp field here.
|
2010-01-21 02:09:26 +00:00
|
|
|
if (ShVal.getNode()->getOpcode() == ISD::ADD &&
|
2008-08-28 21:40:38 +00:00
|
|
|
isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
|
|
|
|
AM.IndexReg = ShVal.getNode()->getOperand(0);
|
2007-12-08 07:22:58 +00:00
|
|
|
ConstantSDNode *AddVal =
|
2008-08-28 21:40:38 +00:00
|
|
|
cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
|
2009-01-17 07:09:27 +00:00
|
|
|
uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
|
2009-08-05 23:01:26 +00:00
|
|
|
if (!is64Bit ||
|
|
|
|
X86::isOffsetSuitableForCodeModel(Disp, M,
|
|
|
|
AM.hasSymbolicDisplacement()))
|
2007-12-08 07:22:58 +00:00
|
|
|
AM.Disp = Disp;
|
|
|
|
else
|
2005-11-19 02:11:08 +00:00
|
|
|
AM.IndexReg = ShVal;
|
2007-12-08 07:22:58 +00:00
|
|
|
} else {
|
|
|
|
AM.IndexReg = ShVal;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
2007-12-08 07:22:58 +00:00
|
|
|
return false;
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
break;
|
2007-12-08 07:22:58 +00:00
|
|
|
}
|
2005-12-08 02:01:35 +00:00
|
|
|
|
2007-10-22 20:22:24 +00:00
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI:
|
|
|
|
// A mul_lohi where we need the low part can be folded as a plain multiply.
|
2008-08-26 22:36:50 +00:00
|
|
|
if (N.getResNo() != 0) break;
|
2007-10-22 20:22:24 +00:00
|
|
|
// FALL THROUGH
|
2005-11-19 02:11:08 +00:00
|
|
|
case ISD::MUL:
|
2009-03-30 21:36:47 +00:00
|
|
|
case X86ISD::MUL_IMM:
|
2005-11-19 02:11:08 +00:00
|
|
|
// X*[3,5,9] -> X+X*[2,4,8]
|
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase &&
|
2008-08-28 21:40:38 +00:00
|
|
|
AM.Base.Reg.getNode() == 0 &&
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
AM.IndexReg.getNode() == 0) {
|
2008-08-31 15:37:04 +00:00
|
|
|
if (ConstantSDNode
|
|
|
|
*CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
|
2008-09-12 16:56:44 +00:00
|
|
|
if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
|
|
|
|
CN->getZExtValue() == 9) {
|
|
|
|
AM.Scale = unsigned(CN->getZExtValue())-1;
|
2005-11-19 02:11:08 +00:00
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
SDValue MulVal = N.getNode()->getOperand(0);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Reg;
|
2005-11-19 02:11:08 +00:00
|
|
|
|
|
|
|
// Okay, we know that we have a scale by now. However, if the scaled
|
|
|
|
// value is an add of something and a constant, we can fold the
|
|
|
|
// constant into the disp field here.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
|
|
|
|
isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
|
|
|
|
Reg = MulVal.getNode()->getOperand(0);
|
2005-11-19 02:11:08 +00:00
|
|
|
ConstantSDNode *AddVal =
|
2008-08-28 21:40:38 +00:00
|
|
|
cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
|
2009-01-17 07:09:27 +00:00
|
|
|
uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
|
2008-09-12 16:56:44 +00:00
|
|
|
CN->getZExtValue();
|
2009-08-05 23:01:26 +00:00
|
|
|
if (!is64Bit ||
|
|
|
|
X86::isOffsetSuitableForCodeModel(Disp, M,
|
|
|
|
AM.hasSymbolicDisplacement()))
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.Disp = Disp;
|
|
|
|
else
|
2008-08-28 21:40:38 +00:00
|
|
|
Reg = N.getNode()->getOperand(0);
|
2005-11-19 02:11:08 +00:00
|
|
|
} else {
|
2008-08-28 21:40:38 +00:00
|
|
|
Reg = N.getNode()->getOperand(0);
|
2005-11-19 02:11:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
AM.IndexReg = AM.Base.Reg = Reg;
|
|
|
|
return false;
|
|
|
|
}
|
2007-02-04 20:18:17 +00:00
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
break;
|
|
|
|
|
2009-05-11 18:02:53 +00:00
|
|
|
case ISD::SUB: {
|
|
|
|
// Given A-B, if A can be completely folded into the address and
|
|
|
|
// the index field with the index field unused, use -B as the index.
|
|
|
|
// This is a win if a has multiple parts that can be folded into
|
|
|
|
// the address. Also, this saves a mov if the base register has
|
|
|
|
// other uses, since it avoids a two-address sub instruction, however
|
|
|
|
// it costs an additional mov if the index register has other uses.
|
|
|
|
|
|
|
|
// Test if the LHS of the sub can be folded.
|
|
|
|
X86ISelAddressMode Backup = AM;
|
2010-03-17 23:58:35 +00:00
|
|
|
if (MatchAddressRecursively(N.getNode()->getOperand(0), AM,
|
|
|
|
DeadNodes, Depth+1) ||
|
|
|
|
// If it is successful but the recursive update causes N to be deleted,
|
|
|
|
// then it's not safe to continue.
|
|
|
|
DeadNodes.IsDeleted(N.getNode())) {
|
2009-05-11 18:02:53 +00:00
|
|
|
AM = Backup;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Test if the index field is free for use.
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
|
2009-05-11 18:02:53 +00:00
|
|
|
AM = Backup;
|
|
|
|
break;
|
|
|
|
}
|
2010-03-17 23:58:35 +00:00
|
|
|
|
2009-05-11 18:02:53 +00:00
|
|
|
int Cost = 0;
|
|
|
|
SDValue RHS = N.getNode()->getOperand(1);
|
|
|
|
// If the RHS involves a register with multiple uses, this
|
|
|
|
// transformation incurs an extra mov, due to the neg instruction
|
|
|
|
// clobbering its operand.
|
|
|
|
if (!RHS.getNode()->hasOneUse() ||
|
|
|
|
RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
|
|
|
|
RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
|
|
|
|
RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
|
|
|
|
(RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
|
2009-08-11 20:47:22 +00:00
|
|
|
RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
|
2009-05-11 18:02:53 +00:00
|
|
|
++Cost;
|
|
|
|
// If the base is a register with multiple uses, this
|
|
|
|
// transformation may save a mov.
|
|
|
|
if ((AM.BaseType == X86ISelAddressMode::RegBase &&
|
|
|
|
AM.Base.Reg.getNode() &&
|
|
|
|
!AM.Base.Reg.getNode()->hasOneUse()) ||
|
|
|
|
AM.BaseType == X86ISelAddressMode::FrameIndexBase)
|
|
|
|
--Cost;
|
|
|
|
// If the folded LHS was interesting, this transformation saves
|
|
|
|
// address arithmetic.
|
|
|
|
if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
|
|
|
|
((AM.Disp != 0) && (Backup.Disp == 0)) +
|
|
|
|
(AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
|
|
|
|
--Cost;
|
|
|
|
// If it doesn't look like it may be an overall win, don't do it.
|
|
|
|
if (Cost >= 0) {
|
|
|
|
AM = Backup;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Ok, the transformation is legal and appears profitable. Go for it.
|
|
|
|
SDValue Zero = CurDAG->getConstant(0, N.getValueType());
|
|
|
|
SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
|
|
|
|
AM.IndexReg = Neg;
|
|
|
|
AM.Scale = 1;
|
|
|
|
|
|
|
|
// Insert the new nodes into the topological ordering.
|
|
|
|
if (Zero.getNode()->getNodeId() == -1 ||
|
|
|
|
Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(N.getNode(), Zero.getNode());
|
|
|
|
Zero.getNode()->setNodeId(N.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (Neg.getNode()->getNodeId() == -1 ||
|
|
|
|
Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(N.getNode(), Neg.getNode());
|
|
|
|
Neg.getNode()->setNodeId(N.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-01-17 07:09:27 +00:00
|
|
|
case ISD::ADD: {
|
|
|
|
X86ISelAddressMode Backup = AM;
|
2010-03-17 23:58:35 +00:00
|
|
|
if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM,
|
|
|
|
DeadNodes, Depth+1)) {
|
|
|
|
if (DeadNodes.IsDeleted(N.getNode()))
|
|
|
|
// If it is successful but the recursive update causes N to be deleted,
|
|
|
|
// then it's not safe to continue.
|
|
|
|
return true;
|
|
|
|
if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM,
|
|
|
|
DeadNodes, Depth+1))
|
|
|
|
// If it is successful but the recursive update causes N to be deleted,
|
|
|
|
// then it's not safe to continue.
|
|
|
|
return DeadNodes.IsDeleted(N.getNode());
|
|
|
|
}
|
|
|
|
|
|
|
|
// Try again after commuting the operands.
|
2009-01-17 07:09:27 +00:00
|
|
|
AM = Backup;
|
2010-03-17 23:58:35 +00:00
|
|
|
if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM,
|
|
|
|
DeadNodes, Depth+1)) {
|
|
|
|
if (DeadNodes.IsDeleted(N.getNode()))
|
|
|
|
// If it is successful but the recursive update causes N to be deleted,
|
|
|
|
// then it's not safe to continue.
|
|
|
|
return true;
|
|
|
|
if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM,
|
|
|
|
DeadNodes, Depth+1))
|
|
|
|
// If it is successful but the recursive update causes N to be deleted,
|
|
|
|
// then it's not safe to continue.
|
|
|
|
return DeadNodes.IsDeleted(N.getNode());
|
|
|
|
}
|
2009-01-17 07:09:27 +00:00
|
|
|
AM = Backup;
|
2009-03-13 02:25:09 +00:00
|
|
|
|
|
|
|
// If we couldn't fold both operands into the address at the same time,
|
|
|
|
// see if we can just put each operand into a register and fold at least
|
|
|
|
// the add.
|
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase &&
|
|
|
|
!AM.Base.Reg.getNode() &&
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
!AM.IndexReg.getNode()) {
|
2009-03-13 02:25:09 +00:00
|
|
|
AM.Base.Reg = N.getNode()->getOperand(0);
|
|
|
|
AM.IndexReg = N.getNode()->getOperand(1);
|
|
|
|
AM.Scale = 1;
|
|
|
|
return false;
|
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
break;
|
2009-01-17 07:09:27 +00:00
|
|
|
}
|
2006-05-30 06:59:36 +00:00
|
|
|
|
2007-02-04 20:18:17 +00:00
|
|
|
case ISD::OR:
|
|
|
|
// Handle "X | C" as "X + C" iff X is known to have C bits clear.
|
2007-12-08 07:22:58 +00:00
|
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
|
|
|
|
X86ISelAddressMode Backup = AM;
|
2008-11-11 15:52:29 +00:00
|
|
|
uint64_t Offset = CN->getSExtValue();
|
2010-03-17 23:58:35 +00:00
|
|
|
|
|
|
|
// Check to see if the LHS & C is zero.
|
|
|
|
if (!CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue()))
|
|
|
|
break;
|
|
|
|
|
2007-12-08 07:22:58 +00:00
|
|
|
// Start with the LHS as an addr mode.
|
2010-03-17 23:58:35 +00:00
|
|
|
if (!MatchAddressRecursively(N.getOperand(0), AM, DeadNodes, Depth+1) &&
|
2007-12-08 07:22:58 +00:00
|
|
|
// Address could not have picked a GV address for the displacement.
|
|
|
|
AM.GV == NULL &&
|
|
|
|
// On x86-64, the resultant disp must fit in 32-bits.
|
2009-08-05 23:01:26 +00:00
|
|
|
(!is64Bit ||
|
|
|
|
X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
|
2010-03-17 23:58:35 +00:00
|
|
|
AM.hasSymbolicDisplacement()))) {
|
2008-11-11 15:52:29 +00:00
|
|
|
AM.Disp += Offset;
|
2007-12-08 07:22:58 +00:00
|
|
|
return false;
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
2007-12-08 07:22:58 +00:00
|
|
|
AM = Backup;
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
|
|
|
break;
|
2007-12-13 00:43:27 +00:00
|
|
|
|
|
|
|
case ISD::AND: {
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
// Perform some heroic transforms on an and of a constant-count shift
|
|
|
|
// with a constant to enable use of the scaled offset field.
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Shift = N.getOperand(0);
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
if (Shift.getNumOperands() != 2) break;
|
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
|
|
|
|
2007-12-13 00:43:27 +00:00
|
|
|
// Scale must not be used already.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
|
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
|
|
|
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
SDValue X = Shift.getOperand(0);
|
2007-12-13 00:43:27 +00:00
|
|
|
ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
|
|
|
|
ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
|
|
|
|
if (!C1 || !C2) break;
|
|
|
|
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
// Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
|
|
|
|
// allows us to convert the shift and and into an h-register extract and
|
|
|
|
// a scaled index.
|
|
|
|
if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
|
|
|
|
unsigned ScaleLog = 8 - C1->getZExtValue();
|
2009-04-16 12:34:53 +00:00
|
|
|
if (ScaleLog > 0 && ScaleLog < 4 &&
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
|
2009-08-11 20:47:22 +00:00
|
|
|
SDValue Eight = CurDAG->getConstant(8, MVT::i8);
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
|
|
|
|
SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
|
|
|
|
X, Eight);
|
|
|
|
SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
|
|
|
|
Srl, Mask);
|
2009-08-11 20:47:22 +00:00
|
|
|
SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
|
2009-04-14 22:45:05 +00:00
|
|
|
SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
|
|
|
|
And, ShlCount);
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
|
|
|
|
// Insert the new nodes into the topological ordering.
|
|
|
|
if (Eight.getNode()->getNodeId() == -1 ||
|
|
|
|
Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(X.getNode(), Eight.getNode());
|
|
|
|
Eight.getNode()->setNodeId(X.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (Mask.getNode()->getNodeId() == -1 ||
|
|
|
|
Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(X.getNode(), Mask.getNode());
|
|
|
|
Mask.getNode()->setNodeId(X.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (Srl.getNode()->getNodeId() == -1 ||
|
|
|
|
Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
|
|
|
|
Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (And.getNode()->getNodeId() == -1 ||
|
|
|
|
And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(N.getNode(), And.getNode());
|
|
|
|
And.getNode()->setNodeId(N.getNode()->getNodeId());
|
|
|
|
}
|
2009-04-14 22:45:05 +00:00
|
|
|
if (ShlCount.getNode()->getNodeId() == -1 ||
|
|
|
|
ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
|
|
|
|
ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (Shl.getNode()->getNodeId() == -1 ||
|
|
|
|
Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(N.getNode(), Shl.getNode());
|
|
|
|
Shl.getNode()->setNodeId(N.getNode()->getNodeId());
|
|
|
|
}
|
2010-03-17 23:58:35 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(N, Shl, &DeadNodes);
|
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 16:09:41 +00:00
|
|
|
AM.IndexReg = And;
|
|
|
|
AM.Scale = (1 << ScaleLog);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
|
|
|
|
// allows us to fold the shift into this addressing mode.
|
|
|
|
if (Shift.getOpcode() != ISD::SHL) break;
|
|
|
|
|
2007-12-13 00:43:27 +00:00
|
|
|
// Not likely to be profitable if either the AND or SHIFT node has more
|
|
|
|
// than one use (unless all uses are for address computation). Besides,
|
|
|
|
// isel mechanism requires their node ids to be reused.
|
|
|
|
if (!N.hasOneUse() || !Shift.hasOneUse())
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Verify that the shift amount is something we can fold.
|
2008-09-12 16:56:44 +00:00
|
|
|
unsigned ShiftCst = C1->getZExtValue();
|
2007-12-13 00:43:27 +00:00
|
|
|
if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
|
|
|
|
break;
|
|
|
|
|
|
|
|
// Get the new AND mask, this folds to a constant.
|
2009-02-03 21:48:12 +00:00
|
|
|
SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
|
2008-10-14 17:15:39 +00:00
|
|
|
SDValue(C2, 0), SDValue(C1, 0));
|
2009-02-03 21:48:12 +00:00
|
|
|
SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
|
|
|
|
NewANDMask);
|
|
|
|
SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
|
2008-10-13 20:52:04 +00:00
|
|
|
NewAND, SDValue(C1, 0));
|
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
|
|
|
|
|
|
|
// Insert the new nodes into the topological ordering.
|
|
|
|
if (C1->getNodeId() > X.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(X.getNode(), C1);
|
|
|
|
C1->setNodeId(X.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (NewANDMask.getNode()->getNodeId() == -1 ||
|
|
|
|
NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
|
|
|
|
NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (NewAND.getNode()->getNodeId() == -1 ||
|
|
|
|
NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
|
|
|
|
NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
if (NewSHIFT.getNode()->getNodeId() == -1 ||
|
|
|
|
NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
|
|
|
|
CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
|
|
|
|
NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
|
|
|
|
}
|
|
|
|
|
2010-03-17 23:58:35 +00:00
|
|
|
CurDAG->ReplaceAllUsesWith(N, NewSHIFT, &DeadNodes);
|
2007-12-13 00:43:27 +00:00
|
|
|
|
|
|
|
AM.Scale = 1 << ShiftCst;
|
|
|
|
AM.IndexReg = NewAND;
|
|
|
|
return false;
|
|
|
|
}
|
2006-05-30 06:59:36 +00:00
|
|
|
}
|
2005-11-19 02:11:08 +00:00
|
|
|
|
2009-03-31 16:16:57 +00:00
|
|
|
return MatchAddressBase(N, AM);
|
2007-08-13 20:03:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
|
|
|
|
/// specified addressing mode without any further recursion.
|
2009-03-31 16:16:57 +00:00
|
|
|
bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
|
2005-11-19 02:11:08 +00:00
|
|
|
// Is the base register already occupied?
|
2008-08-28 21:40:38 +00:00
|
|
|
if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
|
2005-11-19 02:11:08 +00:00
|
|
|
// If so, check to see if the scale index register is set.
|
Reimplement rip-relative addressing in the X86-64 backend. The new
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27 04:16:01 +00:00
|
|
|
if (AM.IndexReg.getNode() == 0) {
|
2005-11-19 02:11:08 +00:00
|
|
|
AM.IndexReg = N;
|
|
|
|
AM.Scale = 1;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we cannot select it.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Default, generate it as a register.
|
|
|
|
AM.BaseType = X86ISelAddressMode::RegBase;
|
|
|
|
AM.Base.Reg = N;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-12-08 02:01:35 +00:00
|
|
|
/// SelectAddr - returns true if it is able pattern match an addressing mode.
|
|
|
|
/// It returns the operands which make up the maximal addressing mode it can
|
|
|
|
/// match by reference.
|
2010-01-05 01:24:18 +00:00
|
|
|
bool X86DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Scale, SDValue &Index,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Disp, SDValue &Segment) {
|
2005-12-08 02:01:35 +00:00
|
|
|
X86ISelAddressMode AM;
|
2009-12-18 01:59:21 +00:00
|
|
|
if (MatchAddress(N, AM))
|
2006-01-11 06:09:51 +00:00
|
|
|
return false;
|
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT VT = N.getValueType();
|
2006-01-11 06:09:51 +00:00
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase) {
|
2008-08-28 21:40:38 +00:00
|
|
|
if (!AM.Base.Reg.getNode())
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, VT);
|
2005-12-08 02:01:35 +00:00
|
|
|
}
|
2006-01-11 06:09:51 +00:00
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
if (!AM.IndexReg.getNode())
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
2006-01-11 06:09:51 +00:00
|
|
|
|
2009-04-08 21:14:34 +00:00
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
|
2006-01-11 06:09:51 +00:00
|
|
|
return true;
|
2005-12-08 02:01:35 +00:00
|
|
|
}
|
|
|
|
|
2006-10-07 21:55:32 +00:00
|
|
|
/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
|
|
|
|
/// match a load whose top elements are either undef or zeros. The load flavor
|
|
|
|
/// is derived from the type of N, which is either v4f32 or v2f64.
|
2010-02-17 06:07:47 +00:00
|
|
|
///
|
|
|
|
/// We also return:
|
2010-02-21 03:17:59 +00:00
|
|
|
/// PatternChainNode: this is the matched node that has a chain input and
|
|
|
|
/// output.
|
2010-03-01 22:51:11 +00:00
|
|
|
bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue N, SDValue &Base,
|
|
|
|
SDValue &Scale, SDValue &Index,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Disp, SDValue &Segment,
|
2010-02-21 03:17:59 +00:00
|
|
|
SDValue &PatternNodeWithChain) {
|
2006-10-07 21:55:32 +00:00
|
|
|
if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
|
2010-02-21 03:17:59 +00:00
|
|
|
PatternNodeWithChain = N.getOperand(0);
|
|
|
|
if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
|
|
|
|
PatternNodeWithChain.hasOneUse() &&
|
2010-02-21 04:53:34 +00:00
|
|
|
IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
|
|
|
|
IsLegalToFold(N.getOperand(0), N.getNode(), Root)) {
|
2010-02-21 03:17:59 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
|
2010-02-16 22:35:06 +00:00
|
|
|
if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp,Segment))
|
2006-10-07 21:55:32 +00:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
|
|
|
|
// Also handle the case where we explicitly require zeros in the top
|
2006-10-07 21:55:32 +00:00
|
|
|
// elements. This is a vector shuffle from the zero vector.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
|
Fix a long standing deficiency in the X86 backend: we would
sometimes emit "zero" and "all one" vectors multiple times,
for example:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
pcmpeqd %mm0, %mm0
movq %mm0, _M2
ret
instead of:
_test2:
pcmpeqd %mm0, %mm0
movq %mm0, _M1
movq %mm0, _M2
ret
This patch fixes this by always arranging for zero/one vectors
to be defined as v4i32 or v2i32 (SSE/MMX) instead of letting them be
any random type. This ensures they get trivially CSE'd on the dag.
This fix is also important for LegalizeDAGTypes, as it gets unhappy
when the x86 backend wants BUILD_VECTOR(i64 0) to be legal even when
'i64' isn't legal.
This patch makes the following changes:
1) X86TargetLowering::LowerBUILD_VECTOR now lowers 0/1 vectors into
their canonical types.
2) The now-dead patterns are removed from the SSE/MMX .td files.
3) All the patterns in the .td file that referred to immAllOnesV or
immAllZerosV in the wrong form now use *_bc to match them with a
bitcast wrapped around them.
4) X86DAGToDAGISel::SelectScalarSSELoad is generalized to handle
bitcast'd zero vectors, which simplifies the code actually.
5) getShuffleVectorZeroOrUndef is updated to generate a shuffle that
is legal, instead of generating one that is illegal and expecting
a later legalize pass to clean it up.
6) isZeroShuffle is generalized to handle bitcast of zeros.
7) several other minor tweaks.
This patch is definite goodness, but has the potential to cause random
code quality regressions. Please be on the lookout for these and let
me know if they happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44310 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-25 00:24:49 +00:00
|
|
|
// Check to see if the top elements are all zeros (or bitcast of zeros).
|
2008-05-08 00:57:18 +00:00
|
|
|
N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
|
2008-08-28 21:40:38 +00:00
|
|
|
N.getOperand(0).getNode()->hasOneUse() &&
|
|
|
|
ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
|
2010-02-16 22:35:06 +00:00
|
|
|
N.getOperand(0).getOperand(0).hasOneUse() &&
|
|
|
|
IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
|
|
|
|
IsLegalToFold(N.getOperand(0), N.getNode(), Root)) {
|
2008-05-08 00:57:18 +00:00
|
|
|
// Okay, this is a zero extending load. Fold it.
|
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
|
2010-02-16 22:35:06 +00:00
|
|
|
if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
|
2008-05-08 00:57:18 +00:00
|
|
|
return false;
|
2010-02-21 03:17:59 +00:00
|
|
|
PatternNodeWithChain = SDValue(LD, 0);
|
2008-05-08 00:57:18 +00:00
|
|
|
return true;
|
Fold "zero extending vector loads" now that evan added the chain manip stuff.
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30894 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-11 22:09:58 +00:00
|
|
|
}
|
2006-10-07 21:55:32 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-02-25 10:09:08 +00:00
|
|
|
/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
|
|
|
|
/// mode it matches can be cost effectively emitted as an LEA instruction.
|
2010-01-05 01:24:18 +00:00
|
|
|
bool X86DAGToDAGISel::SelectLEAAddr(SDNode *Op, SDValue N,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Base, SDValue &Scale,
|
|
|
|
SDValue &Index, SDValue &Disp) {
|
2006-02-25 10:09:08 +00:00
|
|
|
X86ISelAddressMode AM;
|
|
|
|
|
2009-04-10 10:09:34 +00:00
|
|
|
// Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
|
|
|
|
// segments.
|
|
|
|
SDValue Copy = AM.Segment;
|
2009-08-11 20:47:22 +00:00
|
|
|
SDValue T = CurDAG->getRegister(0, MVT::i32);
|
2009-04-10 10:09:34 +00:00
|
|
|
AM.Segment = T;
|
|
|
|
if (MatchAddress(N, AM))
|
2009-04-08 21:14:34 +00:00
|
|
|
return false;
|
2009-04-10 10:09:34 +00:00
|
|
|
assert (T == AM.Segment);
|
|
|
|
AM.Segment = Copy;
|
2009-04-08 21:14:34 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT VT = N.getValueType();
|
2006-02-25 10:09:08 +00:00
|
|
|
unsigned Complexity = 0;
|
|
|
|
if (AM.BaseType == X86ISelAddressMode::RegBase)
|
2008-08-28 21:40:38 +00:00
|
|
|
if (AM.Base.Reg.getNode())
|
2006-02-25 10:09:08 +00:00
|
|
|
Complexity = 1;
|
|
|
|
else
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, VT);
|
2006-02-25 10:09:08 +00:00
|
|
|
else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
|
|
|
|
Complexity = 4;
|
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
if (AM.IndexReg.getNode())
|
2006-02-25 10:09:08 +00:00
|
|
|
Complexity++;
|
|
|
|
else
|
2006-09-08 06:48:29 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(0, VT);
|
2006-02-25 10:09:08 +00:00
|
|
|
|
Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2, #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 06:08:29 +00:00
|
|
|
// Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
|
|
|
|
// a simple shift.
|
|
|
|
if (AM.Scale > 1)
|
2006-02-28 21:13:57 +00:00
|
|
|
Complexity++;
|
2006-02-25 10:09:08 +00:00
|
|
|
|
|
|
|
// FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
|
|
|
|
// to a LEA. This is determined with some expermentation but is by no means
|
|
|
|
// optimal (especially for code size consideration). LEA is nice because of
|
|
|
|
// its three-address nature. Tweak the cost function again when we can run
|
|
|
|
// convertToThreeAddress() at register allocation time.
|
2009-02-07 00:43:41 +00:00
|
|
|
if (AM.hasSymbolicDisplacement()) {
|
2006-09-08 06:48:29 +00:00
|
|
|
// For X86-64, we should always use lea to materialize RIP relative
|
|
|
|
// addresses.
|
2006-12-05 22:03:40 +00:00
|
|
|
if (Subtarget->is64Bit())
|
2006-09-08 06:48:29 +00:00
|
|
|
Complexity = 4;
|
|
|
|
else
|
|
|
|
Complexity += 2;
|
|
|
|
}
|
2006-02-25 10:09:08 +00:00
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
|
2006-02-25 10:09:08 +00:00
|
|
|
Complexity++;
|
|
|
|
|
2009-07-11 22:50:33 +00:00
|
|
|
// If it isn't worth using an LEA, reject it.
|
2009-07-11 23:07:30 +00:00
|
|
|
if (Complexity <= 2)
|
2009-07-11 22:50:33 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue Segment;
|
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
|
|
|
|
return true;
|
2006-02-25 10:09:08 +00:00
|
|
|
}
|
|
|
|
|
2009-06-20 20:38:48 +00:00
|
|
|
/// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
|
2010-01-05 01:24:18 +00:00
|
|
|
bool X86DAGToDAGISel::SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
|
2009-06-20 20:38:48 +00:00
|
|
|
SDValue &Scale, SDValue &Index,
|
|
|
|
SDValue &Disp) {
|
|
|
|
assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
|
|
|
|
const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
|
|
|
|
|
|
|
|
X86ISelAddressMode AM;
|
|
|
|
AM.GV = GA->getGlobal();
|
|
|
|
AM.Disp += GA->getOffset();
|
|
|
|
AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
|
2009-06-26 21:18:37 +00:00
|
|
|
AM.SymbolFlags = GA->getTargetFlags();
|
|
|
|
|
2009-08-11 20:47:22 +00:00
|
|
|
if (N.getValueType() == MVT::i32) {
|
2009-06-20 20:38:48 +00:00
|
|
|
AM.Scale = 1;
|
2009-08-11 20:47:22 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
|
2009-06-20 20:38:48 +00:00
|
|
|
} else {
|
2009-08-11 20:47:22 +00:00
|
|
|
AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
|
2009-06-20 20:38:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDValue Segment;
|
|
|
|
getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-01-05 01:24:18 +00:00
|
|
|
bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Base, SDValue &Scale,
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue &Index, SDValue &Disp,
|
|
|
|
SDValue &Segment) {
|
2010-03-02 22:20:06 +00:00
|
|
|
if (!ISD::isNON_EXTLoad(N.getNode()) ||
|
|
|
|
!IsProfitableToFold(N, P, P) ||
|
|
|
|
!IsLegalToFold(N, P, P))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
|
|
|
|
2008-09-23 18:22:58 +00:00
|
|
|
/// getGlobalBaseReg - Return an SDNode that returns the value of
|
|
|
|
/// the global base register. Output instructions required to
|
|
|
|
/// initialize the global base register, if necessary.
|
2006-02-18 00:15:05 +00:00
|
|
|
///
|
2006-08-26 05:34:46 +00:00
|
|
|
SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
|
2009-06-03 20:20:00 +00:00
|
|
|
unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
|
2008-08-28 21:40:38 +00:00
|
|
|
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
|
2006-02-18 00:15:05 +00:00
|
|
|
}
|
|
|
|
|
2006-05-20 01:36:52 +00:00
|
|
|
static SDNode *FindCallStartFromCall(SDNode *Node) {
|
|
|
|
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
|
2009-08-11 20:47:22 +00:00
|
|
|
assert(Node->getOperand(0).getValueType() == MVT::Other &&
|
2006-05-20 01:36:52 +00:00
|
|
|
"Node doesn't have a token chain argument!");
|
2008-08-28 21:40:38 +00:00
|
|
|
return FindCallStartFromCall(Node->getOperand(0).getNode());
|
2006-05-20 01:36:52 +00:00
|
|
|
}
|
|
|
|
|
2008-10-02 18:53:47 +00:00
|
|
|
SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
|
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
|
|
SDValue In1 = Node->getOperand(1);
|
|
|
|
SDValue In2L = Node->getOperand(2);
|
|
|
|
SDValue In2H = Node->getOperand(3);
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SelectAddr(In1.getNode(), In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
|
2008-10-02 18:53:47 +00:00
|
|
|
return NULL;
|
2009-09-25 20:36:54 +00:00
|
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
|
|
MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
|
|
|
|
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
|
|
|
|
SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
|
|
|
|
MVT::i32, MVT::i32, MVT::Other, Ops,
|
|
|
|
array_lengthof(Ops));
|
|
|
|
cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
|
|
|
|
return ResNode;
|
2008-10-02 18:53:47 +00:00
|
|
|
}
|
2007-08-10 21:48:46 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
|
2009-07-30 08:33:02 +00:00
|
|
|
if (Node->hasAnyUseOfValue(0))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
// Optimize common patterns for __sync_add_and_fetch and
|
|
|
|
// __sync_sub_and_fetch where the result is not used. This allows us
|
|
|
|
// to use "lock" version of add, sub, inc, dec instructions.
|
|
|
|
// FIXME: Do not use special instructions but instead add the "lock"
|
|
|
|
// prefix to the target node somehow. The extra information will then be
|
|
|
|
// transferred to machine instruction and it denotes the prefix.
|
|
|
|
SDValue Chain = Node->getOperand(0);
|
|
|
|
SDValue Ptr = Node->getOperand(1);
|
|
|
|
SDValue Val = Node->getOperand(2);
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SelectAddr(Ptr.getNode(), Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
|
2009-07-30 08:33:02 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
bool isInc = false, isDec = false, isSub = false, isCN = false;
|
|
|
|
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
|
|
|
|
if (CN) {
|
|
|
|
isCN = true;
|
|
|
|
int64_t CNVal = CN->getSExtValue();
|
|
|
|
if (CNVal == 1)
|
|
|
|
isInc = true;
|
|
|
|
else if (CNVal == -1)
|
|
|
|
isDec = true;
|
|
|
|
else if (CNVal >= 0)
|
|
|
|
Val = CurDAG->getTargetConstant(CNVal, NVT);
|
|
|
|
else {
|
|
|
|
isSub = true;
|
|
|
|
Val = CurDAG->getTargetConstant(-CNVal, NVT);
|
|
|
|
}
|
|
|
|
} else if (Val.hasOneUse() &&
|
|
|
|
Val.getOpcode() == ISD::SUB &&
|
|
|
|
X86::isZeroNode(Val.getOperand(0))) {
|
|
|
|
isSub = true;
|
|
|
|
Val = Val.getOperand(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned Opc = 0;
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-07-30 08:33:02 +00:00
|
|
|
default: return 0;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8:
|
2009-07-30 08:33:02 +00:00
|
|
|
if (isInc)
|
|
|
|
Opc = X86::LOCK_INC8m;
|
|
|
|
else if (isDec)
|
|
|
|
Opc = X86::LOCK_DEC8m;
|
|
|
|
else if (isSub) {
|
|
|
|
if (isCN)
|
|
|
|
Opc = X86::LOCK_SUB8mi;
|
|
|
|
else
|
|
|
|
Opc = X86::LOCK_SUB8mr;
|
|
|
|
} else {
|
|
|
|
if (isCN)
|
|
|
|
Opc = X86::LOCK_ADD8mi;
|
|
|
|
else
|
|
|
|
Opc = X86::LOCK_ADD8mr;
|
|
|
|
}
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i16:
|
2009-07-30 08:33:02 +00:00
|
|
|
if (isInc)
|
|
|
|
Opc = X86::LOCK_INC16m;
|
|
|
|
else if (isDec)
|
|
|
|
Opc = X86::LOCK_DEC16m;
|
|
|
|
else if (isSub) {
|
|
|
|
if (isCN) {
|
2010-03-03 01:45:01 +00:00
|
|
|
if (Predicate_immSext8(Val.getNode()))
|
2009-07-30 08:33:02 +00:00
|
|
|
Opc = X86::LOCK_SUB16mi8;
|
|
|
|
else
|
|
|
|
Opc = X86::LOCK_SUB16mi;
|
|
|
|
} else
|
|
|
|
Opc = X86::LOCK_SUB16mr;
|
|
|
|
} else {
|
|
|
|
if (isCN) {
|
2010-03-03 01:45:01 +00:00
|
|
|
if (Predicate_immSext8(Val.getNode()))
|
2009-07-30 08:33:02 +00:00
|
|
|
Opc = X86::LOCK_ADD16mi8;
|
|
|
|
else
|
|
|
|
Opc = X86::LOCK_ADD16mi;
|
|
|
|
} else
|
|
|
|
Opc = X86::LOCK_ADD16mr;
|
|
|
|
}
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i32:
|
2009-07-30 08:33:02 +00:00
|
|
|
if (isInc)
|
|
|
|
Opc = X86::LOCK_INC32m;
|
|
|
|
else if (isDec)
|
|
|
|
Opc = X86::LOCK_DEC32m;
|
|
|
|
else if (isSub) {
|
|
|
|
if (isCN) {
|
2010-03-03 01:45:01 +00:00
|
|
|
if (Predicate_immSext8(Val.getNode()))
|
2009-07-30 08:33:02 +00:00
|
|
|
Opc = X86::LOCK_SUB32mi8;
|
|
|
|
else
|
|
|
|
Opc = X86::LOCK_SUB32mi;
|
|
|
|
} else
|
|
|
|
Opc = X86::LOCK_SUB32mr;
|
|
|
|
} else {
|
|
|
|
if (isCN) {
|
2010-03-03 01:45:01 +00:00
|
|
|
if (Predicate_immSext8(Val.getNode()))
|
2009-07-30 08:33:02 +00:00
|
|
|
Opc = X86::LOCK_ADD32mi8;
|
|
|
|
else
|
|
|
|
Opc = X86::LOCK_ADD32mi;
|
|
|
|
} else
|
|
|
|
Opc = X86::LOCK_ADD32mr;
|
|
|
|
}
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i64:
|
2009-07-30 08:33:02 +00:00
|
|
|
if (isInc)
|
|
|
|
Opc = X86::LOCK_INC64m;
|
|
|
|
else if (isDec)
|
|
|
|
Opc = X86::LOCK_DEC64m;
|
|
|
|
else if (isSub) {
|
|
|
|
Opc = X86::LOCK_SUB64mr;
|
|
|
|
if (isCN) {
|
2010-03-03 01:45:01 +00:00
|
|
|
if (Predicate_immSext8(Val.getNode()))
|
2009-07-30 08:33:02 +00:00
|
|
|
Opc = X86::LOCK_SUB64mi8;
|
|
|
|
else if (Predicate_i64immSExt32(Val.getNode()))
|
|
|
|
Opc = X86::LOCK_SUB64mi32;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
Opc = X86::LOCK_ADD64mr;
|
|
|
|
if (isCN) {
|
2010-03-03 01:45:01 +00:00
|
|
|
if (Predicate_immSext8(Val.getNode()))
|
2009-07-30 08:33:02 +00:00
|
|
|
Opc = X86::LOCK_ADD64mi8;
|
|
|
|
else if (Predicate_i64immSExt32(Val.getNode()))
|
|
|
|
Opc = X86::LOCK_ADD64mi32;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
DebugLoc dl = Node->getDebugLoc();
|
2010-02-09 19:54:29 +00:00
|
|
|
SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
|
2009-09-25 18:54:59 +00:00
|
|
|
dl, NVT), 0);
|
2009-09-25 20:36:54 +00:00
|
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
|
|
MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
|
2009-07-30 08:33:02 +00:00
|
|
|
if (isInc || isDec) {
|
2009-09-25 20:36:54 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
|
|
|
|
SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
|
|
|
|
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
|
2009-07-30 08:33:02 +00:00
|
|
|
SDValue RetVals[] = { Undef, Ret };
|
|
|
|
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
|
|
|
|
} else {
|
2009-09-25 20:36:54 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
|
|
|
|
SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
|
|
|
|
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
|
2009-07-30 08:33:02 +00:00
|
|
|
SDValue RetVals[] = { Undef, Ret };
|
|
|
|
return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-09 20:35:19 +00:00
|
|
|
/// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
|
|
|
|
/// any uses which require the SF or OF bits to be accurate.
|
|
|
|
static bool HasNoSignedComparisonUses(SDNode *N) {
|
|
|
|
// Examine each user of the node.
|
|
|
|
for (SDNode::use_iterator UI = N->use_begin(),
|
|
|
|
UE = N->use_end(); UI != UE; ++UI) {
|
|
|
|
// Only examine CopyToReg uses.
|
|
|
|
if (UI->getOpcode() != ISD::CopyToReg)
|
|
|
|
return false;
|
|
|
|
// Only examine CopyToReg uses that copy to EFLAGS.
|
|
|
|
if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
|
|
|
|
X86::EFLAGS)
|
|
|
|
return false;
|
|
|
|
// Examine each user of the CopyToReg use.
|
|
|
|
for (SDNode::use_iterator FlagUI = UI->use_begin(),
|
|
|
|
FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
|
|
|
|
// Only examine the Flag result.
|
|
|
|
if (FlagUI.getUse().getResNo() != 1) continue;
|
|
|
|
// Anything unusual: assume conservatively.
|
|
|
|
if (!FlagUI->isMachineOpcode()) return false;
|
|
|
|
// Examine the opcode of the user.
|
|
|
|
switch (FlagUI->getMachineOpcode()) {
|
|
|
|
// These comparisons don't treat the most significant bit specially.
|
|
|
|
case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
|
|
|
|
case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
|
|
|
|
case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
|
|
|
|
case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
|
2010-02-11 19:25:55 +00:00
|
|
|
case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
|
|
|
|
case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
|
2009-10-09 20:35:19 +00:00
|
|
|
case X86::CMOVA16rr: case X86::CMOVA16rm:
|
|
|
|
case X86::CMOVA32rr: case X86::CMOVA32rm:
|
|
|
|
case X86::CMOVA64rr: case X86::CMOVA64rm:
|
|
|
|
case X86::CMOVAE16rr: case X86::CMOVAE16rm:
|
|
|
|
case X86::CMOVAE32rr: case X86::CMOVAE32rm:
|
|
|
|
case X86::CMOVAE64rr: case X86::CMOVAE64rm:
|
|
|
|
case X86::CMOVB16rr: case X86::CMOVB16rm:
|
|
|
|
case X86::CMOVB32rr: case X86::CMOVB32rm:
|
|
|
|
case X86::CMOVB64rr: case X86::CMOVB64rm:
|
|
|
|
case X86::CMOVBE16rr: case X86::CMOVBE16rm:
|
|
|
|
case X86::CMOVBE32rr: case X86::CMOVBE32rm:
|
|
|
|
case X86::CMOVBE64rr: case X86::CMOVBE64rm:
|
|
|
|
case X86::CMOVE16rr: case X86::CMOVE16rm:
|
|
|
|
case X86::CMOVE32rr: case X86::CMOVE32rm:
|
|
|
|
case X86::CMOVE64rr: case X86::CMOVE64rm:
|
|
|
|
case X86::CMOVNE16rr: case X86::CMOVNE16rm:
|
|
|
|
case X86::CMOVNE32rr: case X86::CMOVNE32rm:
|
|
|
|
case X86::CMOVNE64rr: case X86::CMOVNE64rm:
|
|
|
|
case X86::CMOVNP16rr: case X86::CMOVNP16rm:
|
|
|
|
case X86::CMOVNP32rr: case X86::CMOVNP32rm:
|
|
|
|
case X86::CMOVNP64rr: case X86::CMOVNP64rm:
|
|
|
|
case X86::CMOVP16rr: case X86::CMOVP16rm:
|
|
|
|
case X86::CMOVP32rr: case X86::CMOVP32rm:
|
|
|
|
case X86::CMOVP64rr: case X86::CMOVP64rm:
|
|
|
|
continue;
|
|
|
|
// Anything else: assume conservatively.
|
|
|
|
default: return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-01-05 01:24:18 +00:00
|
|
|
SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT NVT = Node->getValueType(0);
|
2006-01-06 20:36:21 +00:00
|
|
|
unsigned Opc, MOpc;
|
|
|
|
unsigned Opcode = Node->getOpcode();
|
2009-02-03 21:48:12 +00:00
|
|
|
DebugLoc dl = Node->getDebugLoc();
|
|
|
|
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
|
2006-02-10 22:24:32 +00:00
|
|
|
|
2008-07-17 19:10:17 +00:00
|
|
|
if (Node->isMachineOpcode()) {
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
|
2006-08-11 09:08:15 +00:00
|
|
|
return NULL; // Already selected.
|
2006-02-09 00:37:58 +00:00
|
|
|
}
|
2006-01-11 22:15:18 +00:00
|
|
|
|
2006-01-06 20:36:21 +00:00
|
|
|
switch (Opcode) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: break;
|
|
|
|
case X86ISD::GlobalBaseReg:
|
|
|
|
return getGlobalBaseReg();
|
|
|
|
|
|
|
|
case X86ISD::ATOMOR64_DAG:
|
|
|
|
return SelectAtomic64(Node, X86::ATOMOR6432);
|
|
|
|
case X86ISD::ATOMXOR64_DAG:
|
|
|
|
return SelectAtomic64(Node, X86::ATOMXOR6432);
|
|
|
|
case X86ISD::ATOMADD64_DAG:
|
|
|
|
return SelectAtomic64(Node, X86::ATOMADD6432);
|
|
|
|
case X86ISD::ATOMSUB64_DAG:
|
|
|
|
return SelectAtomic64(Node, X86::ATOMSUB6432);
|
|
|
|
case X86ISD::ATOMNAND64_DAG:
|
|
|
|
return SelectAtomic64(Node, X86::ATOMNAND6432);
|
|
|
|
case X86ISD::ATOMAND64_DAG:
|
|
|
|
return SelectAtomic64(Node, X86::ATOMAND6432);
|
|
|
|
case X86ISD::ATOMSWAP64_DAG:
|
|
|
|
return SelectAtomic64(Node, X86::ATOMSWAP6432);
|
|
|
|
|
|
|
|
case ISD::ATOMIC_LOAD_ADD: {
|
|
|
|
SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
|
|
|
|
if (RetVal)
|
|
|
|
return RetVal;
|
|
|
|
break;
|
|
|
|
}
|
2009-07-30 08:33:02 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
case ISD::SMUL_LOHI:
|
|
|
|
case ISD::UMUL_LOHI: {
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2006-01-06 20:36:21 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
bool isSigned = Opcode == ISD::SMUL_LOHI;
|
2009-08-07 21:33:25 +00:00
|
|
|
if (!isSigned) {
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
|
|
|
|
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
|
|
|
|
case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
|
|
|
|
case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
|
2006-01-06 20:36:21 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
} else {
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
|
|
|
|
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
|
|
|
|
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
|
|
|
|
case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
}
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
unsigned LoReg, HiReg;
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
|
|
|
|
case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
|
|
|
|
case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
|
|
|
|
case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2006-01-06 20:36:21 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
2010-01-05 01:24:18 +00:00
|
|
|
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
2009-08-07 21:33:25 +00:00
|
|
|
// Multiply is commmutative.
|
2009-08-02 16:10:52 +00:00
|
|
|
if (!foldedLoad) {
|
2010-01-05 01:24:18 +00:00
|
|
|
foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
2009-08-02 16:10:52 +00:00
|
|
|
if (foldedLoad)
|
|
|
|
std::swap(N0, N1);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
|
|
|
|
N0, SDValue()).getValue(1);
|
|
|
|
|
|
|
|
if (foldedLoad) {
|
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
|
|
|
|
InFlag };
|
|
|
|
SDNode *CNode =
|
2009-09-25 18:54:59 +00:00
|
|
|
CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
|
|
|
|
array_lengthof(Ops));
|
2009-08-02 16:10:52 +00:00
|
|
|
InFlag = SDValue(CNode, 1);
|
|
|
|
// Update the chain.
|
|
|
|
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
|
|
|
|
} else {
|
|
|
|
InFlag =
|
2009-09-25 18:54:59 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Copy the low half of the result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 0).use_empty()) {
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
LoReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
2010-01-05 01:24:18 +00:00
|
|
|
ReplaceUses(SDValue(Node, 0), Result);
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
// Copy the high half of the result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 1).use_empty()) {
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Result;
|
|
|
|
if (HiReg == X86::AH && Subtarget->is64Bit()) {
|
|
|
|
// Prevent use of AH in a REX instruction by referencing AX instead.
|
|
|
|
// Shift it down 8 bits.
|
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
2009-08-11 20:47:22 +00:00
|
|
|
X86::AX, MVT::i16, InFlag);
|
2009-08-02 16:10:52 +00:00
|
|
|
InFlag = Result.getValue(2);
|
2009-09-25 18:54:59 +00:00
|
|
|
Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
|
|
|
|
Result,
|
2009-08-11 20:47:22 +00:00
|
|
|
CurDAG->getTargetConstant(8, MVT::i8)), 0);
|
2009-08-02 16:10:52 +00:00
|
|
|
// Then truncate it down to i8.
|
2009-08-19 18:16:17 +00:00
|
|
|
Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
|
|
|
|
MVT::i8, Result);
|
2009-08-02 16:10:52 +00:00
|
|
|
} else {
|
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
HiReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
2007-10-08 18:33:35 +00:00
|
|
|
}
|
2010-01-05 01:24:18 +00:00
|
|
|
ReplaceUses(SDValue(Node, 1), Result);
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2006-02-09 00:37:58 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
case ISD::SDIVREM:
|
|
|
|
case ISD::UDIVREM: {
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
bool isSigned = Opcode == ISD::SDIVREM;
|
2009-08-07 21:33:25 +00:00
|
|
|
if (!isSigned) {
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
|
|
|
|
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
|
|
|
|
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
|
|
|
|
case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
} else {
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
|
|
|
|
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
|
|
|
|
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
|
|
|
|
case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
2009-08-07 21:33:25 +00:00
|
|
|
}
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2009-12-23 01:45:04 +00:00
|
|
|
unsigned LoReg, HiReg, ClrReg;
|
2009-08-02 16:10:52 +00:00
|
|
|
unsigned ClrOpcode, SExtOpcode;
|
2009-08-11 20:47:22 +00:00
|
|
|
switch (NVT.getSimpleVT().SimpleTy) {
|
2009-08-02 16:10:52 +00:00
|
|
|
default: llvm_unreachable("Unsupported VT!");
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i8:
|
2009-12-23 01:45:04 +00:00
|
|
|
LoReg = X86::AL; ClrReg = HiReg = X86::AH;
|
2009-08-02 16:10:52 +00:00
|
|
|
ClrOpcode = 0;
|
|
|
|
SExtOpcode = X86::CBW;
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i16:
|
2009-08-02 16:10:52 +00:00
|
|
|
LoReg = X86::AX; HiReg = X86::DX;
|
2010-01-12 04:42:54 +00:00
|
|
|
ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
|
2009-08-02 16:10:52 +00:00
|
|
|
SExtOpcode = X86::CWD;
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i32:
|
2009-12-23 01:45:04 +00:00
|
|
|
LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
|
2009-08-02 16:10:52 +00:00
|
|
|
ClrOpcode = X86::MOV32r0;
|
|
|
|
SExtOpcode = X86::CDQ;
|
|
|
|
break;
|
2009-08-11 20:47:22 +00:00
|
|
|
case MVT::i64:
|
2009-12-23 01:45:04 +00:00
|
|
|
LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
|
2010-01-12 04:42:54 +00:00
|
|
|
ClrOpcode = X86::MOV64r0;
|
2009-08-02 16:10:52 +00:00
|
|
|
SExtOpcode = X86::CQO;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
|
2010-01-05 01:24:18 +00:00
|
|
|
bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
|
2009-08-02 16:10:52 +00:00
|
|
|
bool signBitIsZero = CurDAG->SignBitIsZero(N0);
|
|
|
|
|
|
|
|
SDValue InFlag;
|
2009-08-11 20:47:22 +00:00
|
|
|
if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
|
2009-08-02 16:10:52 +00:00
|
|
|
// Special case for div8, just use a move with zero extension to AX to
|
|
|
|
// clear the upper 8 bits (AH).
|
|
|
|
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
|
2010-01-05 01:24:18 +00:00
|
|
|
if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
|
|
|
|
Move =
|
2009-09-25 18:54:59 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16,
|
|
|
|
MVT::Other, Ops,
|
|
|
|
array_lengthof(Ops)), 0);
|
2009-08-02 16:10:52 +00:00
|
|
|
Chain = Move.getValue(1);
|
|
|
|
ReplaceUses(N0.getValue(1), Chain);
|
2006-11-17 22:10:14 +00:00
|
|
|
} else {
|
2009-08-02 16:10:52 +00:00
|
|
|
Move =
|
2009-09-25 18:54:59 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
|
2009-08-02 16:10:52 +00:00
|
|
|
Chain = CurDAG->getEntryNode();
|
|
|
|
}
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
} else {
|
|
|
|
InFlag =
|
|
|
|
CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
|
|
|
|
LoReg, N0, SDValue()).getValue(1);
|
|
|
|
if (isSigned && !signBitIsZero) {
|
|
|
|
// Sign extend the low part into the high part.
|
2006-11-17 22:10:14 +00:00
|
|
|
InFlag =
|
2009-09-25 18:54:59 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
|
2009-08-02 16:10:52 +00:00
|
|
|
} else {
|
|
|
|
// Zero out the high part, effectively zero extending the input.
|
2010-01-12 04:42:54 +00:00
|
|
|
SDValue ClrNode =
|
|
|
|
SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
|
2009-12-23 01:45:04 +00:00
|
|
|
InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
|
2009-08-02 16:10:52 +00:00
|
|
|
ClrNode, InFlag).getValue(1);
|
2006-01-06 23:19:29 +00:00
|
|
|
}
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
2006-01-06 23:19:29 +00:00
|
|
|
|
2009-08-02 16:10:52 +00:00
|
|
|
if (foldedLoad) {
|
|
|
|
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
|
|
|
|
InFlag };
|
|
|
|
SDNode *CNode =
|
2009-09-25 18:54:59 +00:00
|
|
|
CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
|
|
|
|
array_lengthof(Ops));
|
2009-08-02 16:10:52 +00:00
|
|
|
InFlag = SDValue(CNode, 1);
|
|
|
|
// Update the chain.
|
|
|
|
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
|
|
|
|
} else {
|
|
|
|
InFlag =
|
2009-09-25 18:54:59 +00:00
|
|
|
SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Copy the division (low) result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 0).use_empty()) {
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
LoReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
2010-01-05 01:24:18 +00:00
|
|
|
ReplaceUses(SDValue(Node, 0), Result);
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
// Copy the remainder (high) result, if it is needed.
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SDValue(Node, 1).use_empty()) {
|
2009-08-02 16:10:52 +00:00
|
|
|
SDValue Result;
|
|
|
|
if (HiReg == X86::AH && Subtarget->is64Bit()) {
|
|
|
|
// Prevent use of AH in a REX instruction by referencing AX instead.
|
|
|
|
// Shift it down 8 bits.
|
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
2009-08-11 20:47:22 +00:00
|
|
|
X86::AX, MVT::i16, InFlag);
|
2009-08-02 16:10:52 +00:00
|
|
|
InFlag = Result.getValue(2);
|
2009-09-25 18:54:59 +00:00
|
|
|
Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
|
2009-08-02 16:10:52 +00:00
|
|
|
Result,
|
2009-08-11 20:47:22 +00:00
|
|
|
CurDAG->getTargetConstant(8, MVT::i8)),
|
2009-08-02 16:10:52 +00:00
|
|
|
0);
|
|
|
|
// Then truncate it down to i8.
|
2009-08-19 18:16:17 +00:00
|
|
|
Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
|
|
|
|
MVT::i8, Result);
|
2009-08-02 16:10:52 +00:00
|
|
|
} else {
|
|
|
|
Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
|
|
|
|
HiReg, NVT, InFlag);
|
|
|
|
InFlag = Result.getValue(2);
|
2007-09-25 18:23:27 +00:00
|
|
|
}
|
2010-01-05 01:24:18 +00:00
|
|
|
ReplaceUses(SDValue(Node, 1), Result);
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
|
2009-08-02 16:10:52 +00:00
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2009-08-19 18:16:17 +00:00
|
|
|
case X86ISD::CMP: {
|
|
|
|
SDValue N0 = Node->getOperand(0);
|
|
|
|
SDValue N1 = Node->getOperand(1);
|
|
|
|
|
|
|
|
// Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
|
|
|
|
// use a smaller encoding.
|
|
|
|
if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
|
|
|
|
N0.getValueType() != MVT::i8 &&
|
|
|
|
X86::isZeroNode(N1)) {
|
|
|
|
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
|
|
|
|
if (!C) break;
|
|
|
|
|
|
|
|
// For example, convert "testl %eax, $8" to "testb %al, $8"
|
2009-10-09 20:35:19 +00:00
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
|
|
|
|
(!(C->getZExtValue() & 0x80) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// On x86-32, only the ABCD registers have 8-bit subregisters.
|
|
|
|
if (!Subtarget->is64Bit()) {
|
|
|
|
TargetRegisterClass *TRC = 0;
|
|
|
|
switch (N0.getValueType().getSimpleVT().SimpleTy) {
|
|
|
|
case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
|
|
|
|
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
|
|
|
|
default: llvm_unreachable("Unsupported TEST operand type!");
|
|
|
|
}
|
|
|
|
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
|
2009-09-25 18:54:59 +00:00
|
|
|
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
|
|
|
|
Reg.getValueType(), Reg, RC), 0);
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Extract the l-register.
|
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
|
|
|
|
MVT::i8, Reg);
|
|
|
|
|
|
|
|
// Emit a testb.
|
2009-09-25 18:54:59 +00:00
|
|
|
return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// For example, "testl %eax, $2048" to "testb %ah, $8".
|
2009-10-09 20:35:19 +00:00
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
|
|
|
|
(!(C->getZExtValue() & 0x8000) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
// Shift the immediate right by 8 bits.
|
|
|
|
SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
|
|
|
|
MVT::i8);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// Put the value in an ABCD register.
|
|
|
|
TargetRegisterClass *TRC = 0;
|
|
|
|
switch (N0.getValueType().getSimpleVT().SimpleTy) {
|
|
|
|
case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
|
|
|
|
case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
|
|
|
|
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
|
|
|
|
default: llvm_unreachable("Unsupported TEST operand type!");
|
|
|
|
}
|
|
|
|
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
|
2009-09-25 18:54:59 +00:00
|
|
|
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
|
|
|
|
Reg.getValueType(), Reg, RC), 0);
|
2009-08-19 18:16:17 +00:00
|
|
|
|
|
|
|
// Extract the h-register.
|
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl,
|
|
|
|
MVT::i8, Reg);
|
|
|
|
|
|
|
|
// Emit a testb. No special NOREX tricks are needed since there's
|
|
|
|
// only one GPR operand!
|
2009-09-25 18:54:59 +00:00
|
|
|
return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
|
|
|
|
Subreg, ShiftedImm);
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// For example, "testl %eax, $32776" to "testw %ax, $32776".
|
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
|
2009-10-09 20:35:19 +00:00
|
|
|
N0.getValueType() != MVT::i16 &&
|
|
|
|
(!(C->getZExtValue() & 0x8000) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// Extract the 16-bit subregister.
|
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_16BIT, dl,
|
|
|
|
MVT::i16, Reg);
|
|
|
|
|
|
|
|
// Emit a testw.
|
2009-09-25 18:54:59 +00:00
|
|
|
return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// For example, "testq %rax, $268468232" to "testl %eax, $268468232".
|
|
|
|
if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
|
2009-10-09 20:35:19 +00:00
|
|
|
N0.getValueType() == MVT::i64 &&
|
|
|
|
(!(C->getZExtValue() & 0x80000000) ||
|
|
|
|
HasNoSignedComparisonUses(Node))) {
|
2009-08-19 18:16:17 +00:00
|
|
|
SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
|
|
SDValue Reg = N0.getNode()->getOperand(0);
|
|
|
|
|
|
|
|
// Extract the 32-bit subregister.
|
|
|
|
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_32BIT, dl,
|
|
|
|
MVT::i32, Reg);
|
|
|
|
|
|
|
|
// Emit a testl.
|
2009-09-25 18:54:59 +00:00
|
|
|
return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
|
2009-08-19 18:16:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
2010-01-05 01:24:18 +00:00
|
|
|
SDNode *ResNode = SelectCode(Node);
|
2006-08-11 09:08:15 +00:00
|
|
|
|
2010-03-02 06:34:30 +00:00
|
|
|
DEBUG(dbgs() << "=> ";
|
|
|
|
if (ResNode == NULL || ResNode == Node)
|
|
|
|
Node->dump(CurDAG);
|
|
|
|
else
|
|
|
|
ResNode->dump(CurDAG);
|
|
|
|
dbgs() << '\n');
|
2006-08-11 09:08:15 +00:00
|
|
|
|
|
|
|
return ResNode;
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|
|
|
|
|
2006-06-08 18:03:49 +00:00
|
|
|
bool X86DAGToDAGISel::
|
2008-07-27 21:46:04 +00:00
|
|
|
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
|
2008-08-23 02:25:05 +00:00
|
|
|
std::vector<SDValue> &OutOps) {
|
2009-04-08 21:14:34 +00:00
|
|
|
SDValue Op0, Op1, Op2, Op3, Op4;
|
2006-06-08 18:03:49 +00:00
|
|
|
switch (ConstraintCode) {
|
|
|
|
case 'o': // offsetable ??
|
|
|
|
case 'v': // not offsetable ??
|
|
|
|
default: return true;
|
|
|
|
case 'm': // memory
|
2010-01-05 01:24:18 +00:00
|
|
|
if (!SelectAddr(Op.getNode(), Op, Op0, Op1, Op2, Op3, Op4))
|
2006-06-08 18:03:49 +00:00
|
|
|
return true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2006-08-26 01:05:16 +00:00
|
|
|
OutOps.push_back(Op0);
|
|
|
|
OutOps.push_back(Op1);
|
|
|
|
OutOps.push_back(Op2);
|
|
|
|
OutOps.push_back(Op3);
|
2009-04-08 21:14:34 +00:00
|
|
|
OutOps.push_back(Op4);
|
2006-06-08 18:03:49 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-11-16 01:54:32 +00:00
|
|
|
/// createX86ISelDag - This pass converts a legalized DAG into a
|
|
|
|
/// X86-specific DAG, ready for instruction scheduling.
|
|
|
|
///
|
2009-04-29 23:29:43 +00:00
|
|
|
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
|
|
|
|
llvm::CodeGenOpt::Level OptLevel) {
|
2009-04-29 00:15:41 +00:00
|
|
|
return new X86DAGToDAGISel(TM, OptLevel);
|
2005-11-16 01:54:32 +00:00
|
|
|
}
|