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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
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"http://www.w3.org/TR/html4/strict.dtd">
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<html>
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<head>
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<title>The LLVM Target-Independent Code Generator</title>
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<link rel="stylesheet" href="llvm.css" type="text/css">
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</head>
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<body>
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<div class="doc_title">
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The LLVM Target-Independent Code Generator
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</div>
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<ol>
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<li><a href="#introduction">Introduction</a>
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<ul>
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<li><a href="#required">Required components in the code generator</a></li>
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<li><a href="#high-level-design">The high-level design of the code generator</a></li>
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<li><a href="#tablegen">Using TableGen for target description</a></li>
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</ul>
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</li>
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<li><a href="#targetdesc">Target description classes</a>
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<ul>
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<li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
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<li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
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<li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
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<li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
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<li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
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<li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
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</ul>
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</li>
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<li><a href="#codegendesc">Machine code description classes</a>
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<ul>
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<li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
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</ul>
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</li>
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<li><a href="#codegenalgs">Target-independent code generation algorithms</a>
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</li>
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<li><a href="#targetimpls">Target description implementations</a>
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<ul>
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<li><a href="#x86">The X86 backend</a></li>
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</ul>
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</li>
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</ol>
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<div class="doc_author">
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<p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
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</div>
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2004-06-01 17:18:11 +00:00
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<div class="doc_warning">
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<p>Warning: This is a work in progress.</p>
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</div>
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2004-06-01 06:48:00 +00:00
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="introduction">Introduction</a>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_text">
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<p>The LLVM target-independent code generator is a framework that provides a
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suite of reusable components for translating the LLVM internal representation to
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the machine code for a specified target -- either in assembly form (suitable for
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a static compiler) or in binary machine code format (usable for a JIT compiler).
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The LLVM target-independent code generator consists of five main components:</p>
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<ol>
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<li><a href="#targetdesc">Abstract target description</a> interfaces which
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capture important properties about various aspects of the machine, independently
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of how they will be used. These interfaces are defined in
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<tt>include/llvm/Target/</tt>.</li>
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<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
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generated for a target. These classes are intended to be abstract enough to
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represent the machine code for <i>any</i> target machine. These classes are
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defined in <tt>include/llvm/CodeGen/</tt>.</li>
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<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
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various phases of native code generation (register allocation, scheduling, stack
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frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
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<li><a href="#targetimpls">Implementations of the abstract target description
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interfaces</a> for particular targets. These machine descriptions make use of
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the components provided by LLVM, and can optionally provide custom
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target-specific passes, to build complete code generators for a specific target.
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Target descriptions live in <tt>lib/Target/</tt>.</li>
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<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
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completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
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interface for target-specific issues. The code for the target-independent
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JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
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</ol>
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<p>
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Depending on which part of the code generator you are interested in working on,
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different pieces of this will be useful to you. In any case, you should be
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familiar with the <a href="#targetdesc">target description</a> and <a
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href="#codegendesc">machine code representation</a> classes. If you want to add
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a backend for a new target, you will need to <a href="#targetimpls">implement the
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target description</a> classes for your new target and understand the <a
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href="LangRef.html">LLVM code representation</a>. If you are interested in
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implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
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should only depend on the target-description and machine code representation
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classes, ensuring that it is portable.
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</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="required">Required components in the code generator</a>
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</div>
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<div class="doc_text">
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<p>The two pieces of the LLVM code generator are the high-level interface to the
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code generator and the set of reusable components that can be used to build
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target-specific backends. The two most important interfaces (<a
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href="#targetmachine"><tt>TargetMachine</tt></a> and <a
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href="#targetdata"><tt>TargetData</tt></a> classes) are the only ones that are
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required to be defined for a backend to fit into the LLVM system, but the others
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must be defined if the reusable code generator components are going to be
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used.</p>
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<p>This design has two important implications. The first is that LLVM can
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support completely non-traditional code generation targets. For example, the C
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backend does not require register allocation, instruction selection, or any of
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the other standard components provided by the system. As such, it only
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implements these two interfaces, and does its own thing. Another example of a
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code generator like this is a (purely hypothetical) backend that converts LLVM
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to the GCC RTL form and uses GCC to emit machine code for a target.</p>
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<p>This design also implies that it is possible to design and
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implement radically different code generators in the LLVM system that do not
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make use of any of the built-in components. Doing so is not recommended at all,
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but could be required for radically different targets that do not fit into the
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LLVM machine description model: programmable FPGAs for example.</p>
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2004-06-02 07:06:06 +00:00
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<p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
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generator uses almost entirely different code paths than described in this
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document. For this reason, there are some deprecated interfaces (such as
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<tt>TargetRegInfo</tt> and <tt>TargetSchedInfo</tt>), which are only used by the
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V9 backend and should not be used by any other targets. Also, all code in the
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<tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
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deprecated, and should not be used as the basis for future code generator work.
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The SparcV9 backend is slowly being merged into the rest of the
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target-independent code generators, but this is a low-priority process with no
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predictable completion date.</p>
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2004-06-01 06:48:00 +00:00
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="high-level-design">The high-level design of the code generator</a>
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</div>
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<div class="doc_text">
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<p>The LLVM target-indendent code generator is designed to support efficient and
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quality code generation for standard register-based microprocessors. Code
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generation in this model is divided into the following stages:</p>
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<ol>
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<li><b>Instruction Selection</b> - Determining an efficient implementation of the
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input LLVM code in the target instruction set. This stage produces the initial
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code for the program in the target instruction set, then makes use of virtual
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registers in SSA form and physical registers that represent any required
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register assignments due to target constraints or calling conventions.</li>
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<li><b>SSA-based Machine Code Optimizations</b> - This (optional) stage consists
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of a series of machine-code optimizations that operate on the SSA-form produced
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by the instruction selector. Optimizations like modulo-scheduling, normal
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scheduling, or peephole optimization work here.</li>
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<li><b>Register Allocation</b> - The target code is transformed from an infinite
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virtual register file in SSA form to the concrete register file used by the
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target. This phase introduces spill code and eliminates all virtual register
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references from the program.</li>
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<li><b>Prolog/Epilog Code Insertion</b> - Once the machine code has been
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generated for the function and the amount of stack space required is known (used
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for LLVM alloca's and spill slots), the prolog and epilog code for the function
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can be inserted and "abstract stack location references" can be eliminated.
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This stage is responsible for implementing optimizations like frame-pointer
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elimination and stack packing.</li>
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<li><b>Late Machine Code Optimizations</b> - Optimizations that operate on
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"final" machine code can go here, such as spill code scheduling and peephole
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optimizations.</li>
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<li><b>Code Emission</b> - The final stage actually outputs the code for
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the current function, either in the target assembler format or in machine
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code.</li>
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</ol>
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<p>
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The code generator is based on the assumption that the instruction selector will
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use an optimal pattern matching selector to create high-quality sequences of
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native instructions. Alternative code generator designs based on pattern
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expansion and
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aggressive iterative peephole optimization are much slower. This design
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permits efficient compilation (important for JIT environments) and
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aggressive optimization (used when generating code offline) by allowing
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components of varying levels of sophisication to be used for any step of
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compilation.</p>
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<p>
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In addition to these stages, target implementations can insert arbitrary
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target-specific passes into the flow. For example, the X86 target uses a
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special pass to handle the 80x87 floating point stack architecture. Other
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targets with unusual requirements can be supported with custom passes as needed.
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</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="tablegen">Using TableGen for target description</a>
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</div>
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<div class="doc_text">
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2004-06-01 18:35:00 +00:00
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<p>The target description classes require a detailed description of the target
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architecture. These target descriptions often have a large amount of common
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information (e.g., an add instruction is almost identical to a sub instruction).
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In order to allow the maximum amount of commonality to be factored out, the LLVM
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code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
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describe big chunks of the target machine, which allows the use of domain- and
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target-specific abstractions to reduce the amount of repetition.
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</p>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="targetdesc">Target description classes</a>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_text">
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<p>The LLVM target description classes (which are located in the
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<tt>include/llvm/Target</tt> directory) provide an abstract description of the
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target machine, independent of any particular client. These classes are
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designed to capture the <i>abstract</i> properties of the target (such as what
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instruction and registers it has), and do not incorporate any particular pieces
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of code generation algorithms (these interfaces do not take interference graphs
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as inputs or other algorithm-specific data structures).</p>
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<p>All of the target description classes (except the <tt><a
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href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
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the concrete target implementation, and have virtual methods implemented. To
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get to these implementations, the <tt><a
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href="#targetmachine">TargetMachine</a></tt> class provides accessors that
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should be implemented by the target.</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="targetmachine">The <tt>TargetMachine</tt> class</a>
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</div>
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<div class="doc_text">
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<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
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access the target-specific implementations of the various target description
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classes (with the <tt>getInstrInfo</tt>, <tt>getRegisterInfo</tt>,
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<tt>getFrameInfo</tt>, ... methods). This class is designed to be specialized by
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a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
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implements the various virtual methods. The only required target description
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class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
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code generator components are to be used, the other interfaces should be
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implemented as well.</p>
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</div>
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|
|
|
|
|
|
|
|
|
|
|
|
|
<!-- ======================================================================= -->
|
|
|
|
|
<div class="doc_subsection">
|
|
|
|
|
<a name="targetdata">The <tt>TargetData</tt> class</a>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>The <tt>TargetData</tt> class is the only required target description class,
|
|
|
|
|
and it is the only class that is not extensible (it cannot be derived from). It
|
|
|
|
|
specifies information about how the target lays out memory for structures, the
|
|
|
|
|
alignment requirements for various data types, the size of pointers in the
|
|
|
|
|
target, and whether the target is little- or big-endian.</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<!-- ======================================================================= -->
|
|
|
|
|
<div class="doc_subsection">
|
2004-06-01 17:18:11 +00:00
|
|
|
<a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
|
2004-06-01 06:48:00 +00:00
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
|
|
|
|
|
<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
|
|
|
|
|
target and any interactions between the registers.</p>
|
|
|
|
|
|
|
|
|
|
<p>Registers in the code generator are represented in the code generator by
|
|
|
|
|
unsigned numbers. Physical registers (those that actually exist in the target
|
|
|
|
|
description) are unique small numbers, and virtual registers are generally
|
|
|
|
|
large.</p>
|
|
|
|
|
|
|
|
|
|
<p>Each register in the processor description has an associated
|
|
|
|
|
<tt>MRegisterDesc</tt> entry, which provides a textual name for the register
|
|
|
|
|
(used for assembly output and debugging dumps), a set of aliases (used to
|
|
|
|
|
indicate that one register overlaps with another), and some flag bits.
|
|
|
|
|
</p>
|
|
|
|
|
|
|
|
|
|
<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
|
|
|
|
|
exposes a set of processor specific register classes (instances of the
|
|
|
|
|
<tt>TargetRegisterClass</tt> class). Each register class contains sets of
|
|
|
|
|
registers that have the same properties (for example, they are all 32-bit
|
|
|
|
|
integer registers). Each SSA virtual register created by the instruction
|
|
|
|
|
selector has an associated register class. When the register allocator runs, it
|
|
|
|
|
replaces virtual registers with a physical register in the set.</p>
|
|
|
|
|
|
|
|
|
|
<p>
|
|
|
|
|
The target-specific implementations of these classes is auto-generated from a <a
|
|
|
|
|
href="TableGenFundamentals.html">TableGen</a> description of the register file.
|
|
|
|
|
</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- ======================================================================= -->
|
|
|
|
|
<div class="doc_subsection">
|
2004-06-01 17:18:11 +00:00
|
|
|
<a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
|
2004-06-01 06:48:00 +00:00
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- ======================================================================= -->
|
|
|
|
|
<div class="doc_subsection">
|
2004-06-01 17:18:11 +00:00
|
|
|
<a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
|
2004-06-01 06:48:00 +00:00
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- ======================================================================= -->
|
|
|
|
|
<div class="doc_subsection">
|
2004-06-01 17:18:11 +00:00
|
|
|
<a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
|
2004-06-01 06:48:00 +00:00
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- *********************************************************************** -->
|
|
|
|
|
<div class="doc_section">
|
|
|
|
|
<a name="codegendesc">Machine code description classes</a>
|
|
|
|
|
</div>
|
|
|
|
|
<!-- *********************************************************************** -->
|
|
|
|
|
|
2004-06-04 00:16:02 +00:00
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>
|
|
|
|
|
At the high-level, LLVM code is translated to a machine specific representation
|
|
|
|
|
formed out of MachineFunction, MachineBasicBlock, and <a
|
|
|
|
|
href="#machineinstr"><tt>MachineInstr</tt></a> instances
|
|
|
|
|
(defined in include/llvm/CodeGen). This representation is completely target
|
|
|
|
|
agnostic, representing instructions in their most abstract form: an opcode and a
|
|
|
|
|
series of operands. This representation is designed to support both SSA
|
|
|
|
|
representation for machine code, as well as a register allocated, non-SSA form.
|
|
|
|
|
</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- ======================================================================= -->
|
|
|
|
|
<div class="doc_subsection">
|
|
|
|
|
<a name="machineinstr">The <tt>MachineInstr</tt> class</a>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>Target machine instructions are represented as instances of the
|
|
|
|
|
<tt>MachineInstr</tt> class. This class is an extremely abstract way of
|
|
|
|
|
representing machine instructions. In particular, all it keeps track of is
|
|
|
|
|
an opcode number and some number of operands.</p>
|
|
|
|
|
|
|
|
|
|
<p>The opcode number is an simple unsigned number that only has meaning to a
|
|
|
|
|
specific backend. All of the instructions for a target should be defined in
|
|
|
|
|
the <tt>*InstrInfo.td</tt> file for the target, and the opcode enum values
|
|
|
|
|
are autogenerated from this description. The <tt>MachineInstr</tt> class does
|
|
|
|
|
not have any information about how to intepret the instruction (i.e., what the
|
|
|
|
|
semantics of the instruction are): for that you must refer to the
|
|
|
|
|
<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
|
|
|
|
|
|
|
|
|
|
<p>The operands of a machine instruction can be of several different types:
|
|
|
|
|
they can be a register reference, constant integer, basic block reference, etc.
|
|
|
|
|
In addition, a machine operand should be marked as a def or a use of the value
|
|
|
|
|
(though only registers are allowed to be defs).</p>
|
|
|
|
|
|
|
|
|
|
<p>By convention, the LLVM code generator orders instruction operands so that
|
|
|
|
|
all register definitions come before the register uses, even on architectures
|
|
|
|
|
that are normally printed in other orders. For example, the sparc add
|
|
|
|
|
instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
|
|
|
|
|
and stores the result into the "%i3" register. In the LLVM code generator,
|
|
|
|
|
the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
|
|
|
|
|
first.</p>
|
|
|
|
|
|
|
|
|
|
<p>Keeping destination operands at the beginning of the operand list has several
|
|
|
|
|
advantages. In particular, the debugging printer will print the instruction
|
|
|
|
|
like this:</p>
|
|
|
|
|
|
|
|
|
|
<pre>
|
|
|
|
|
%r3 = add %i1, %i2
|
|
|
|
|
</pre>
|
|
|
|
|
|
|
|
|
|
<p>If the first operand is a def, and it is also easier to <a
|
|
|
|
|
href="#buildmi">create instructions</a> whose only def is the first
|
|
|
|
|
operand.</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- _______________________________________________________________________ -->
|
|
|
|
|
<div class="doc_subsubsection">
|
|
|
|
|
<a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
|
|
|
|
|
located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
|
|
|
|
|
<tt>BuildMI</tt> functions make it easy to build arbitrary machine
|
|
|
|
|
instructions. Usage of the <tt>BuildMI</tt> functions look like this:
|
|
|
|
|
</p>
|
|
|
|
|
|
|
|
|
|
<pre>
|
|
|
|
|
// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
|
|
|
|
|
// instruction. The '1' specifies how many operands will be added.
|
|
|
|
|
MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
|
|
|
|
|
|
|
|
|
|
// Create the same instr, but insert it at the end of a basic block.
|
|
|
|
|
MachineBasicBlock &MBB = ...
|
|
|
|
|
BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
|
|
|
|
|
|
|
|
|
|
// Create the same instr, but insert it before a specified iterator point.
|
|
|
|
|
MachineBasicBlock::iterator MBBI = ...
|
|
|
|
|
BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
|
|
|
|
|
|
|
|
|
|
// Create a 'cmp Reg, 0' instruction, no destination reg.
|
|
|
|
|
MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
|
|
|
|
|
// Create an 'sahf' instruction which takes no operands and stores nothing.
|
|
|
|
|
MI = BuildMI(X86::SAHF, 0);
|
|
|
|
|
|
|
|
|
|
// Create a self looping branch instruction.
|
|
|
|
|
BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
|
|
|
|
|
</pre>
|
|
|
|
|
|
|
|
|
|
<p>
|
|
|
|
|
The key thing to remember with the <tt>BuildMI</tt> functions is that you have
|
|
|
|
|
to specify the number of operands that the machine instruction will take
|
|
|
|
|
(allowing efficient memory allocation). Also, if operands default to be uses
|
|
|
|
|
of values, not definitions. If you need to add a definition operand (other
|
|
|
|
|
than the optional destination register), you must explicitly mark it as such.
|
|
|
|
|
</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- _______________________________________________________________________ -->
|
|
|
|
|
<div class="doc_subsubsection">
|
|
|
|
|
<a name="fixedregs">Fixed (aka preassigned) registers</a>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>One important issue that the code generator needs to be aware of is the
|
|
|
|
|
presence of fixed registers. In particular, there are often places in the
|
|
|
|
|
instruction stream where the register allocator <em>must</em> arrange for a
|
|
|
|
|
particular value to be in a particular register. This can occur due to
|
|
|
|
|
limitations in the instruction set (e.g., the X86 can only do a 32-bit divide
|
|
|
|
|
with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
|
|
|
|
|
conventions. In any case, the instruction selector should emit code that
|
|
|
|
|
copies a virtual register into or out of a physical register when needed.</p>
|
|
|
|
|
|
|
|
|
|
<p>For example, consider this simple LLVM example:</p>
|
|
|
|
|
|
|
|
|
|
<pre>
|
|
|
|
|
int %test(int %X, int %Y) {
|
|
|
|
|
%Z = div int %X, %Y
|
|
|
|
|
ret int %Z
|
|
|
|
|
}
|
|
|
|
|
</pre>
|
|
|
|
|
|
|
|
|
|
<p>The X86 instruction selector produces this machine code for the div
|
|
|
|
|
and ret (use
|
|
|
|
|
"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
|
|
|
|
|
|
|
|
|
|
<pre>
|
|
|
|
|
;; Start of div
|
|
|
|
|
%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
|
|
|
|
|
%reg1027 = sar %reg1024, 31
|
|
|
|
|
%EDX = mov %reg1027 ;; Sign extend X into EDX
|
|
|
|
|
idiv %reg1025 ;; Divide by Y (in reg1025)
|
|
|
|
|
%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
|
|
|
|
|
|
|
|
|
|
;; Start of ret
|
|
|
|
|
%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
|
|
|
|
|
ret
|
|
|
|
|
</pre>
|
|
|
|
|
|
|
|
|
|
<p>By the end of code generation, the register allocator has coallesced
|
|
|
|
|
the registers and deleted the resultant identity moves, producing the
|
|
|
|
|
following code:</p>
|
|
|
|
|
|
|
|
|
|
<pre>
|
|
|
|
|
;; X is in EAX, Y is in ECX
|
|
|
|
|
mov %EAX, %EDX
|
|
|
|
|
sar %EDX, 31
|
|
|
|
|
idiv %ECX
|
|
|
|
|
ret
|
|
|
|
|
</pre>
|
|
|
|
|
|
|
|
|
|
<p>This approach is extremely general (if it can handle the X86 architecture,
|
|
|
|
|
it can handle anything!) and allows all of the target specific
|
|
|
|
|
knowledge about the instruction stream to be isolated in the instruction
|
|
|
|
|
selector. Note that physical registers should have a short lifetime for good
|
|
|
|
|
code generation, and all physical registers are assumed dead on entry and
|
|
|
|
|
exit of basic blocks (before register allocation). Thus if you need a value
|
|
|
|
|
to be live across basic block boundaries, it <em>must</em> live in a virtual
|
|
|
|
|
register.</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- _______________________________________________________________________ -->
|
|
|
|
|
<div class="doc_subsubsection">
|
|
|
|
|
<a name="ssa">Machine code SSA form</a>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
2004-06-01 06:48:00 +00:00
|
|
|
|
2004-06-04 00:16:02 +00:00
|
|
|
<p><tt>MachineInstr</tt>'s are initially instruction selected in SSA-form, and
|
|
|
|
|
are maintained in SSA-form until register allocation happens. For the most
|
|
|
|
|
part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
|
|
|
|
|
become machine code PHI nodes, and virtual registers are only allowed to have a
|
|
|
|
|
single definition.</p>
|
|
|
|
|
|
|
|
|
|
<p>After register allocation, machine code is no longer in SSA-form, as there
|
|
|
|
|
are no virtual registers left in the code.</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- *********************************************************************** -->
|
|
|
|
|
<div class="doc_section">
|
|
|
|
|
<a name="targetimpls">Target description implementations</a>
|
|
|
|
|
</div>
|
|
|
|
|
<!-- *********************************************************************** -->
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>This section of the document explains any features or design decisions that
|
|
|
|
|
are specific to the code generator for a particular target.</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<!-- ======================================================================= -->
|
|
|
|
|
<div class="doc_subsection">
|
|
|
|
|
<a name="x86">The X86 backend</a>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>
|
|
|
|
|
The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
|
|
|
|
|
code generator currently targets a generic P6-like processor. As such, it
|
|
|
|
|
produces a few P6-and-above instructions (like conditional moves), but it does
|
|
|
|
|
not make use of newer features like MMX or SSE. In the future, the X86 backend
|
|
|
|
|
will have subtarget support added for specific processor families and
|
|
|
|
|
implementations.</p>
|
|
|
|
|
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<!-- _______________________________________________________________________ -->
|
|
|
|
|
<div class="doc_subsubsection">
|
|
|
|
|
<a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
|
|
|
|
|
</div>
|
|
|
|
|
|
|
|
|
|
<div class="doc_text">
|
|
|
|
|
|
|
|
|
|
<p>
|
|
|
|
|
The x86 has a very, uhm, flexible, way of accessing memory. It is capable of
|
|
|
|
|
forming memory addresses of the following expression directly in integer
|
|
|
|
|
instructions (which use ModR/M addressing):</p>
|
|
|
|
|
|
|
|
|
|
<pre>
|
|
|
|
|
Base+[1,2,4,8]*IndexReg+Disp32
|
|
|
|
|
</pre>
|
|
|
|
|
|
2004-12-03 15:59:26 +00:00
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<p>Wow, that's crazy. In order to represent this, LLVM tracks no less than 4
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2004-06-04 00:16:02 +00:00
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operands for each memory operand of this form. This means that the "load" form
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of 'mov' has the following "Operands" in this order:</p>
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<pre>
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Index: 0 | 1 2 3 4
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Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
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OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
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</pre>
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<p>Stores and all other instructions treat the four memory operands in the same
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way, in the same order.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="x86_names">Instruction naming</a>
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</div>
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<div class="doc_text">
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<p>
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An instruction name consists of the base name, a default operand size
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followed by a character per operand with an optional special size. For
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example:</p>
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<p>
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<tt>ADD8rr</tt> -> add, 8-bit register, 8-bit register<br>
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<tt>IMUL16rmi</tt> -> imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
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<tt>IMUL16rmi8</tt> -> imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
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<tt>MOVSX32rm16</tt> -> movsx, 32-bit register, 16-bit memory
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</p>
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</div>
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2004-06-01 06:48:00 +00:00
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<!-- *********************************************************************** -->
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<a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
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<a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
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Last modified: $Date$
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