llvm-6502/test/CodeGen/ARM/ldrd.ll

; RUN: llc < %s -mtriple=armv6-apple-darwin | grep ldrd
; RUN: llc < %s -mtriple=armv5-apple-darwin | not grep ldrd
; RUN: llc < %s -mtriple=armv6-eabi | not grep ldrd
; rdar://r6949835

@b = external global i64*

define i64 @t(i64 %a) nounwind readonly {
entry:
	%0 = load i64** @b, align 4
	%1 = load i64* %0, align 4
	%2 = mul i64 %1, %a
	ret i64 %2
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-09 00:09:15 +00:00			`; RUN: llc < %s -mtriple=armv6-apple-darwin \| grep ldrd`
			`; RUN: llc < %s -mtriple=armv5-apple-darwin \| not grep ldrd`
			`; RUN: llc < %s -mtriple=armv6-eabi \| not grep ldrd`
Part 1. - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed before register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-15 08:28:29 +00:00			`; rdar://r6949835`

			`@b = external global i64*`

			`define i64 @t(i64 %a) nounwind readonly {`
			`entry:`
			`%0 = load i64** @b, align 4`
			`%1 = load i64* %0, align 4`
			`%2 = mul i64 %1, %a`
			`ret i64 %2`
			`}`