mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
305 lines
12 KiB
C++
305 lines
12 KiB
C++
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//===-- Mos6502AsmBackend.cpp - Mos6502 Assembler Backend ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCAsmBackend.h"
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#include "MCTargetDesc/Mos6502FixupKinds.h"
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#include "MCTargetDesc/Mos6502MCTargetDesc.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return Value;
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case Mos6502::fixup_mos6502_wplt30:
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case Mos6502::fixup_mos6502_call30:
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return (Value >> 2) & 0x3fffffff;
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case Mos6502::fixup_mos6502_br22:
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return (Value >> 2) & 0x3fffff;
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case Mos6502::fixup_mos6502_br19:
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return (Value >> 2) & 0x7ffff;
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case Mos6502::fixup_mos6502_br16_2:
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return (Value >> 2) & 0xc000;
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case Mos6502::fixup_mos6502_br16_14:
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return (Value >> 2) & 0x3fff;
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case Mos6502::fixup_mos6502_pc22:
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case Mos6502::fixup_mos6502_got22:
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case Mos6502::fixup_mos6502_tls_gd_hi22:
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case Mos6502::fixup_mos6502_tls_ldm_hi22:
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case Mos6502::fixup_mos6502_tls_ie_hi22:
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case Mos6502::fixup_mos6502_hi22:
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return (Value >> 10) & 0x3fffff;
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case Mos6502::fixup_mos6502_pc10:
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case Mos6502::fixup_mos6502_got10:
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case Mos6502::fixup_mos6502_tls_gd_lo10:
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case Mos6502::fixup_mos6502_tls_ldm_lo10:
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case Mos6502::fixup_mos6502_tls_ie_lo10:
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case Mos6502::fixup_mos6502_lo10:
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return Value & 0x3ff;
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case Mos6502::fixup_mos6502_tls_ldo_hix22:
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case Mos6502::fixup_mos6502_tls_le_hix22:
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return (~Value >> 10) & 0x3fffff;
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case Mos6502::fixup_mos6502_tls_ldo_lox10:
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case Mos6502::fixup_mos6502_tls_le_lox10:
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return (~(~Value & 0x3ff)) & 0x1fff;
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case Mos6502::fixup_mos6502_h44:
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return (Value >> 22) & 0x3fffff;
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case Mos6502::fixup_mos6502_m44:
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return (Value >> 12) & 0x3ff;
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case Mos6502::fixup_mos6502_l44:
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return Value & 0xfff;
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case Mos6502::fixup_mos6502_hh:
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return (Value >> 42) & 0x3fffff;
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case Mos6502::fixup_mos6502_hm:
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return (Value >> 32) & 0x3ff;
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case Mos6502::fixup_mos6502_tls_gd_add:
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case Mos6502::fixup_mos6502_tls_gd_call:
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case Mos6502::fixup_mos6502_tls_ldm_add:
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case Mos6502::fixup_mos6502_tls_ldm_call:
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case Mos6502::fixup_mos6502_tls_ldo_add:
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case Mos6502::fixup_mos6502_tls_ie_ld:
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case Mos6502::fixup_mos6502_tls_ie_ldx:
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case Mos6502::fixup_mos6502_tls_ie_add:
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return 0;
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}
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}
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namespace {
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class Mos6502AsmBackend : public MCAsmBackend {
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protected:
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const Target &TheTarget;
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bool IsLittleEndian;
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bool Is64Bit;
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public:
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Mos6502AsmBackend(const Target &T)
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: MCAsmBackend(), TheTarget(T),
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IsLittleEndian(StringRef(TheTarget.getName()) == "mos6502el"),
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Is64Bit(StringRef(TheTarget.getName()) == "mos6502v9") {}
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unsigned getNumFixupKinds() const override {
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return Mos6502::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo InfosBE[Mos6502::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_mos6502_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_hi22", 10, 22, 0 },
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{ "fixup_mos6502_lo10", 22, 10, 0 },
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{ "fixup_mos6502_h44", 10, 22, 0 },
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{ "fixup_mos6502_m44", 22, 10, 0 },
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{ "fixup_mos6502_l44", 20, 12, 0 },
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{ "fixup_mos6502_hh", 10, 22, 0 },
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{ "fixup_mos6502_hm", 22, 10, 0 },
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{ "fixup_mos6502_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_got22", 10, 22, 0 },
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{ "fixup_mos6502_got10", 22, 10, 0 },
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{ "fixup_mos6502_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_tls_gd_hi22", 10, 22, 0 },
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{ "fixup_mos6502_tls_gd_lo10", 22, 10, 0 },
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{ "fixup_mos6502_tls_gd_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_gd_call", 0, 0, 0 },
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{ "fixup_mos6502_tls_ldm_hi22", 10, 22, 0 },
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{ "fixup_mos6502_tls_ldm_lo10", 22, 10, 0 },
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{ "fixup_mos6502_tls_ldm_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_ldm_call", 0, 0, 0 },
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{ "fixup_mos6502_tls_ldo_hix22", 10, 22, 0 },
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{ "fixup_mos6502_tls_ldo_lox10", 22, 10, 0 },
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{ "fixup_mos6502_tls_ldo_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_ie_hi22", 10, 22, 0 },
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{ "fixup_mos6502_tls_ie_lo10", 22, 10, 0 },
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{ "fixup_mos6502_tls_ie_ld", 0, 0, 0 },
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{ "fixup_mos6502_tls_ie_ldx", 0, 0, 0 },
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{ "fixup_mos6502_tls_ie_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_le_hix22", 0, 0, 0 },
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{ "fixup_mos6502_tls_le_lox10", 0, 0, 0 }
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};
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const static MCFixupKindInfo InfosLE[Mos6502::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_mos6502_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_hi22", 0, 22, 0 },
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{ "fixup_mos6502_lo10", 0, 10, 0 },
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{ "fixup_mos6502_h44", 0, 22, 0 },
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{ "fixup_mos6502_m44", 0, 10, 0 },
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{ "fixup_mos6502_l44", 0, 12, 0 },
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{ "fixup_mos6502_hh", 0, 22, 0 },
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{ "fixup_mos6502_hm", 0, 10, 0 },
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{ "fixup_mos6502_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_got22", 0, 22, 0 },
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{ "fixup_mos6502_got10", 0, 10, 0 },
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{ "fixup_mos6502_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_mos6502_tls_gd_hi22", 0, 22, 0 },
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{ "fixup_mos6502_tls_gd_lo10", 0, 10, 0 },
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{ "fixup_mos6502_tls_gd_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_gd_call", 0, 0, 0 },
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{ "fixup_mos6502_tls_ldm_hi22", 0, 22, 0 },
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{ "fixup_mos6502_tls_ldm_lo10", 0, 10, 0 },
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{ "fixup_mos6502_tls_ldm_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_ldm_call", 0, 0, 0 },
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{ "fixup_mos6502_tls_ldo_hix22", 0, 22, 0 },
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{ "fixup_mos6502_tls_ldo_lox10", 0, 10, 0 },
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{ "fixup_mos6502_tls_ldo_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_ie_hi22", 0, 22, 0 },
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{ "fixup_mos6502_tls_ie_lo10", 0, 10, 0 },
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{ "fixup_mos6502_tls_ie_ld", 0, 0, 0 },
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{ "fixup_mos6502_tls_ie_ldx", 0, 0, 0 },
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{ "fixup_mos6502_tls_ie_add", 0, 0, 0 },
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{ "fixup_mos6502_tls_le_hix22", 0, 0, 0 },
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{ "fixup_mos6502_tls_le_lox10", 0, 0, 0 }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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if (IsLittleEndian)
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return InfosLE[Kind - FirstTargetFixupKind];
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return InfosBE[Kind - FirstTargetFixupKind];
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}
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void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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const MCValue &Target, uint64_t &Value,
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bool &IsResolved) override {
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switch ((Mos6502::Fixups)Fixup.getKind()) {
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default: break;
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case Mos6502::fixup_mos6502_wplt30:
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if (Target.getSymA()->getSymbol().isTemporary())
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return;
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case Mos6502::fixup_mos6502_tls_gd_hi22:
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case Mos6502::fixup_mos6502_tls_gd_lo10:
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case Mos6502::fixup_mos6502_tls_gd_add:
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case Mos6502::fixup_mos6502_tls_gd_call:
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case Mos6502::fixup_mos6502_tls_ldm_hi22:
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case Mos6502::fixup_mos6502_tls_ldm_lo10:
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case Mos6502::fixup_mos6502_tls_ldm_add:
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case Mos6502::fixup_mos6502_tls_ldm_call:
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case Mos6502::fixup_mos6502_tls_ldo_hix22:
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case Mos6502::fixup_mos6502_tls_ldo_lox10:
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case Mos6502::fixup_mos6502_tls_ldo_add:
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case Mos6502::fixup_mos6502_tls_ie_hi22:
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case Mos6502::fixup_mos6502_tls_ie_lo10:
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case Mos6502::fixup_mos6502_tls_ie_ld:
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case Mos6502::fixup_mos6502_tls_ie_ldx:
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case Mos6502::fixup_mos6502_tls_ie_add:
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case Mos6502::fixup_mos6502_tls_le_hix22:
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case Mos6502::fixup_mos6502_tls_le_lox10: IsResolved = false; break;
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}
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}
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bool mayNeedRelaxation(const MCInst &Inst) const override {
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// FIXME.
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return false;
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}
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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/// fixup requires the associated instruction to be relaxed.
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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// FIXME.
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llvm_unreachable("fixupNeedsRelaxation() unimplemented");
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return false;
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}
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
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// FIXME.
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llvm_unreachable("relaxInstruction() unimplemented");
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}
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
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// Cannot emit NOP with size not multiple of 32 bits.
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if (Count % 4 != 0)
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return false;
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->write32(0x01000000);
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return true;
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}
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};
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class ELFMos6502AsmBackend : public Mos6502AsmBackend {
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Triple::OSType OSType;
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public:
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ELFMos6502AsmBackend(const Target &T, Triple::OSType OSType) :
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Mos6502AsmBackend(T), OSType(OSType) { }
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value, bool IsPCRel) const override {
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Value = adjustFixupValue(Fixup.getKind(), Value);
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if (!Value) return; // Doesn't change encoding.
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unsigned Offset = Fixup.getOffset();
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// For each byte of the fragment that the fixup touches, mask in the bits
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// from the fixup value. The Value has been "split up" into the
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// appropriate bitfields above.
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for (unsigned i = 0; i != 4; ++i) {
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unsigned Idx = IsLittleEndian ? i : 3 - i;
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Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
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}
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}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
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return createMos6502ELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI);
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}
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};
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} // end anonymous namespace
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MCAsmBackend *llvm::createMos6502AsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
|
||
|
|
const Triple &TT, StringRef CPU) {
|
||
|
|
return new ELFMos6502AsmBackend(T, TT.getOS());
|
||
|
|
}
|