mirror of
https://github.com/c64scene-ar/llvm-6502.git
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450 lines
17 KiB
C++
450 lines
17 KiB
C++
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//===-- Mos6502AsmPrinter.cpp - Mos6502 LLVM assembly writer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MOS6502 assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "Mos6502.h"
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#include "InstPrinter/Mos6502InstPrinter.h"
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#include "MCTargetDesc/Mos6502MCExpr.h"
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#include "Mos6502InstrInfo.h"
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#include "Mos6502TargetMachine.h"
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#include "Mos6502TargetStreamer.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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namespace {
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class Mos6502AsmPrinter : public AsmPrinter {
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Mos6502TargetStreamer &getTargetStreamer() {
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return static_cast<Mos6502TargetStreamer &>(
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*OutStreamer->getTargetStreamer());
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}
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public:
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explicit Mos6502AsmPrinter(TargetMachine &TM,
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std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)) {}
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const char *getPassName() const override {
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return "Mos6502 Assembly Printer";
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}
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
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const char *Modifier = nullptr);
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void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
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void EmitFunctionBodyStart() override;
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void EmitInstruction(const MachineInstr *MI) override;
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static const char *getRegisterName(unsigned RegNo) {
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return Mos6502InstPrinter::getRegisterName(RegNo);
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}
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) override;
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) override;
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void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
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const MCSubtargetInfo &STI);
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};
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} // end of anonymous namespace
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static MCOperand createMos6502MCOperand(Mos6502MCExpr::VariantKind Kind,
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MCSymbol *Sym, MCContext &OutContext) {
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym,
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OutContext);
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const Mos6502MCExpr *expr = Mos6502MCExpr::create(Kind, MCSym, OutContext);
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return MCOperand::createExpr(expr);
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}
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static MCOperand createPCXCallOP(MCSymbol *Label,
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MCContext &OutContext) {
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return createMos6502MCOperand(Mos6502MCExpr::VK_Mos6502_None, Label, OutContext);
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}
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static MCOperand createPCXRelExprOp(Mos6502MCExpr::VariantKind Kind,
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MCSymbol *GOTLabel, MCSymbol *StartLabel,
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MCSymbol *CurLabel,
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MCContext &OutContext)
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{
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const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
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const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
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OutContext);
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const MCSymbolRefExpr *Cur = MCSymbolRefExpr::create(CurLabel,
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OutContext);
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const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
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const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
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const Mos6502MCExpr *expr = Mos6502MCExpr::create(Kind,
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Add, OutContext);
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return MCOperand::createExpr(expr);
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}
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static void EmitCall(MCStreamer &OutStreamer,
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MCOperand &Callee,
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const MCSubtargetInfo &STI)
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{
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MCInst CallInst;
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CallInst.setOpcode(SP::CALL);
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CallInst.addOperand(Callee);
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OutStreamer.EmitInstruction(CallInst, STI);
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}
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static void EmitSETHI(MCStreamer &OutStreamer,
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MCOperand &Imm, MCOperand &RD,
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const MCSubtargetInfo &STI)
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{
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MCInst SETHIInst;
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SETHIInst.setOpcode(SP::SETHIi);
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SETHIInst.addOperand(RD);
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SETHIInst.addOperand(Imm);
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OutStreamer.EmitInstruction(SETHIInst, STI);
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}
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static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
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MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
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const MCSubtargetInfo &STI)
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{
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MCInst Inst;
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Inst.setOpcode(Opcode);
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Inst.addOperand(RD);
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Inst.addOperand(RS1);
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Inst.addOperand(Src2);
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OutStreamer.EmitInstruction(Inst, STI);
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}
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static void EmitOR(MCStreamer &OutStreamer,
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MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
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const MCSubtargetInfo &STI) {
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EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
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}
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static void EmitADD(MCStreamer &OutStreamer,
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MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
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const MCSubtargetInfo &STI) {
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EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
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}
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static void EmitSHL(MCStreamer &OutStreamer,
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MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
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const MCSubtargetInfo &STI) {
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EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
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}
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static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
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Mos6502MCExpr::VariantKind HiKind,
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Mos6502MCExpr::VariantKind LoKind,
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MCOperand &RD,
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MCContext &OutContext,
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const MCSubtargetInfo &STI) {
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MCOperand hi = createMos6502MCOperand(HiKind, GOTSym, OutContext);
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MCOperand lo = createMos6502MCOperand(LoKind, GOTSym, OutContext);
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EmitSETHI(OutStreamer, hi, RD, STI);
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EmitOR(OutStreamer, RD, lo, RD, STI);
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}
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void Mos6502AsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
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const MCSubtargetInfo &STI)
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{
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MCSymbol *GOTLabel =
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OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.getReg() != SP::O7 &&
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"%o7 is assigned as destination for getpcx!");
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MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
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if (TM.getRelocationModel() != Reloc::PIC_) {
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// Just load the address of GOT to MCRegOP.
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switch(TM.getCodeModel()) {
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default:
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llvm_unreachable("Unsupported absolute code model");
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case CodeModel::Small:
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EmitHiLo(*OutStreamer, GOTLabel,
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Mos6502MCExpr::VK_Mos6502_HI, Mos6502MCExpr::VK_Mos6502_LO,
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MCRegOP, OutContext, STI);
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break;
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case CodeModel::Medium: {
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EmitHiLo(*OutStreamer, GOTLabel,
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Mos6502MCExpr::VK_Mos6502_H44, Mos6502MCExpr::VK_Mos6502_M44,
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MCRegOP, OutContext, STI);
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MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(12,
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OutContext));
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EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
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MCOperand lo = createMos6502MCOperand(Mos6502MCExpr::VK_Mos6502_L44,
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GOTLabel, OutContext);
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EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI);
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break;
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}
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case CodeModel::Large: {
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EmitHiLo(*OutStreamer, GOTLabel,
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Mos6502MCExpr::VK_Mos6502_HH, Mos6502MCExpr::VK_Mos6502_HM,
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MCRegOP, OutContext, STI);
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MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(32,
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OutContext));
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EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
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// Use register %o7 to load the lower 32 bits.
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MCOperand RegO7 = MCOperand::createReg(SP::O7);
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EmitHiLo(*OutStreamer, GOTLabel,
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Mos6502MCExpr::VK_Mos6502_HI, Mos6502MCExpr::VK_Mos6502_LO,
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RegO7, OutContext, STI);
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EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
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}
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}
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return;
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}
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MCSymbol *StartLabel = OutContext.createTempSymbol();
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MCSymbol *EndLabel = OutContext.createTempSymbol();
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MCSymbol *SethiLabel = OutContext.createTempSymbol();
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MCOperand RegO7 = MCOperand::createReg(SP::O7);
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// <StartLabel>:
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// call <EndLabel>
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// <SethiLabel>:
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// sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
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// <EndLabel>:
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// or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
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// add <MO>, %o7, <MO>
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OutStreamer->EmitLabel(StartLabel);
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MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
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EmitCall(*OutStreamer, Callee, STI);
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OutStreamer->EmitLabel(SethiLabel);
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MCOperand hiImm = createPCXRelExprOp(Mos6502MCExpr::VK_Mos6502_PC22,
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GOTLabel, StartLabel, SethiLabel,
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OutContext);
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EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
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OutStreamer->EmitLabel(EndLabel);
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MCOperand loImm = createPCXRelExprOp(Mos6502MCExpr::VK_Mos6502_PC10,
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GOTLabel, StartLabel, EndLabel,
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OutContext);
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EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
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EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
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}
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void Mos6502AsmPrinter::EmitInstruction(const MachineInstr *MI)
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{
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switch (MI->getOpcode()) {
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default: break;
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case TargetOpcode::DBG_VALUE:
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// FIXME: Debug Value.
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return;
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case SP::GETPCX:
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LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
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return;
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}
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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MCInst TmpInst;
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LowerMos6502MachineInstrToMCInst(I, TmpInst, *this);
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EmitToStreamer(*OutStreamer, TmpInst);
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} while ((++I != E) && I->isInsideBundle()); // Delay slot check.
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}
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void Mos6502AsmPrinter::EmitFunctionBodyStart() {
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if (!MF->getSubtarget<Mos6502Subtarget>().is64Bit())
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return;
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
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for (unsigned i = 0; globalRegs[i] != 0; ++i) {
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unsigned reg = globalRegs[i];
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if (MRI.use_empty(reg))
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continue;
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if (reg == SP::G6 || reg == SP::G7)
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getTargetStreamer().emitMos6502RegisterIgnore(reg);
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else
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getTargetStreamer().emitMos6502RegisterScratch(reg);
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}
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}
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void Mos6502AsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const DataLayout &DL = getDataLayout();
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const MachineOperand &MO = MI->getOperand (opNum);
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Mos6502MCExpr::VariantKind TF = (Mos6502MCExpr::VariantKind) MO.getTargetFlags();
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#ifndef NDEBUG
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// Verify the target flags.
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if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
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if (MI->getOpcode() == SP::CALL)
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assert(TF == Mos6502MCExpr::VK_Mos6502_None &&
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"Cannot handle target flags on call address");
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else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
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assert((TF == Mos6502MCExpr::VK_Mos6502_HI
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|| TF == Mos6502MCExpr::VK_Mos6502_H44
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|| TF == Mos6502MCExpr::VK_Mos6502_HH
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|| TF == Mos6502MCExpr::VK_Mos6502_TLS_GD_HI22
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|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LDM_HI22
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|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LDO_HIX22
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|| TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_HI22
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|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LE_HIX22) &&
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"Invalid target flags for address operand on sethi");
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else if (MI->getOpcode() == SP::TLS_CALL)
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assert((TF == Mos6502MCExpr::VK_Mos6502_None
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|| TF == Mos6502MCExpr::VK_Mos6502_TLS_GD_CALL
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|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LDM_CALL) &&
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"Cannot handle target flags on tls call address");
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else if (MI->getOpcode() == SP::TLS_ADDrr)
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assert((TF == Mos6502MCExpr::VK_Mos6502_TLS_GD_ADD
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LDM_ADD
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LDO_ADD
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_ADD) &&
|
||
|
|
"Cannot handle target flags on add for TLS");
|
||
|
|
else if (MI->getOpcode() == SP::TLS_LDrr)
|
||
|
|
assert(TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_LD &&
|
||
|
|
"Cannot handle target flags on ld for TLS");
|
||
|
|
else if (MI->getOpcode() == SP::TLS_LDXrr)
|
||
|
|
assert(TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_LDX &&
|
||
|
|
"Cannot handle target flags on ldx for TLS");
|
||
|
|
else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
|
||
|
|
assert((TF == Mos6502MCExpr::VK_Mos6502_TLS_LDO_LOX10
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LE_LOX10) &&
|
||
|
|
"Cannot handle target flags on xor for TLS");
|
||
|
|
else
|
||
|
|
assert((TF == Mos6502MCExpr::VK_Mos6502_LO
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_M44
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_L44
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_HM
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_TLS_GD_LO10
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_TLS_LDM_LO10
|
||
|
|
|| TF == Mos6502MCExpr::VK_Mos6502_TLS_IE_LO10 ) &&
|
||
|
|
"Invalid target flags for small address operand");
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
bool CloseParen = Mos6502MCExpr::printVariantKind(O, TF);
|
||
|
|
|
||
|
|
switch (MO.getType()) {
|
||
|
|
case MachineOperand::MO_Register:
|
||
|
|
O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case MachineOperand::MO_Immediate:
|
||
|
|
O << (int)MO.getImm();
|
||
|
|
break;
|
||
|
|
case MachineOperand::MO_MachineBasicBlock:
|
||
|
|
MO.getMBB()->getSymbol()->print(O, MAI);
|
||
|
|
return;
|
||
|
|
case MachineOperand::MO_GlobalAddress:
|
||
|
|
getSymbol(MO.getGlobal())->print(O, MAI);
|
||
|
|
break;
|
||
|
|
case MachineOperand::MO_BlockAddress:
|
||
|
|
O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
|
||
|
|
break;
|
||
|
|
case MachineOperand::MO_ExternalSymbol:
|
||
|
|
O << MO.getSymbolName();
|
||
|
|
break;
|
||
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
||
|
|
O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
|
||
|
|
<< MO.getIndex();
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
llvm_unreachable("<unknown operand type>");
|
||
|
|
}
|
||
|
|
if (CloseParen) O << ")";
|
||
|
|
}
|
||
|
|
|
||
|
|
void Mos6502AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
|
||
|
|
raw_ostream &O, const char *Modifier) {
|
||
|
|
printOperand(MI, opNum, O);
|
||
|
|
|
||
|
|
// If this is an ADD operand, emit it like normal operands.
|
||
|
|
if (Modifier && !strcmp(Modifier, "arith")) {
|
||
|
|
O << ", ";
|
||
|
|
printOperand(MI, opNum+1, O);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (MI->getOperand(opNum+1).isReg() &&
|
||
|
|
MI->getOperand(opNum+1).getReg() == SP::G0)
|
||
|
|
return; // don't print "+%g0"
|
||
|
|
if (MI->getOperand(opNum+1).isImm() &&
|
||
|
|
MI->getOperand(opNum+1).getImm() == 0)
|
||
|
|
return; // don't print "+0"
|
||
|
|
|
||
|
|
O << "+";
|
||
|
|
printOperand(MI, opNum+1, O);
|
||
|
|
}
|
||
|
|
|
||
|
|
/// PrintAsmOperand - Print out an operand for an inline asm expression.
|
||
|
|
///
|
||
|
|
bool Mos6502AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
|
||
|
|
unsigned AsmVariant,
|
||
|
|
const char *ExtraCode,
|
||
|
|
raw_ostream &O) {
|
||
|
|
if (ExtraCode && ExtraCode[0]) {
|
||
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
||
|
|
|
||
|
|
switch (ExtraCode[0]) {
|
||
|
|
default:
|
||
|
|
// See if this is a generic print operand
|
||
|
|
return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
|
||
|
|
case 'r':
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
printOperand(MI, OpNo, O);
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool Mos6502AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
||
|
|
unsigned OpNo, unsigned AsmVariant,
|
||
|
|
const char *ExtraCode,
|
||
|
|
raw_ostream &O) {
|
||
|
|
if (ExtraCode && ExtraCode[0])
|
||
|
|
return true; // Unknown modifier
|
||
|
|
|
||
|
|
O << '[';
|
||
|
|
printMemOperand(MI, OpNo, O);
|
||
|
|
O << ']';
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Force static initialization.
|
||
|
|
extern "C" void LLVMInitializeMos6502AsmPrinter() {
|
||
|
|
RegisterAsmPrinter<Mos6502AsmPrinter> X(TheMos6502Target);
|
||
|
|
RegisterAsmPrinter<Mos6502AsmPrinter> Y(TheMos6502V9Target);
|
||
|
|
RegisterAsmPrinter<Mos6502AsmPrinter> Z(TheMos6502elTarget);
|
||
|
|
}
|