2012-02-18 12:03:15 +00:00
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//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
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2009-07-08 17:28:55 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the base ARM implementation of TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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2012-03-17 07:33:42 +00:00
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#include "ARMBaseRegisterInfo.h"
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2009-07-08 17:28:55 +00:00
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#include "ARM.h"
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2009-07-08 18:31:39 +00:00
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#include "ARMBaseInstrInfo.h"
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2011-01-10 12:39:04 +00:00
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#include "ARMFrameLowering.h"
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2009-07-08 17:28:55 +00:00
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSubtarget.h"
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2011-07-20 23:34:39 +00:00
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#include "MCTargetDesc/ARMAddressingModes.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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2009-07-08 17:28:55 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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2012-12-03 22:35:35 +00:00
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#include "llvm/CodeGen/VirtRegMap.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/LLVMContext.h"
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2009-10-27 22:45:39 +00:00
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#include "llvm/Support/Debug.h"
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2009-07-08 18:01:40 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/raw_ostream.h"
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2011-01-10 12:39:04 +00:00
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#include "llvm/Target/TargetFrameLowering.h"
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2009-07-08 17:28:55 +00:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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2011-06-27 18:32:37 +00:00
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#define GET_REGINFO_TARGET_DESC
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2011-06-24 01:44:41 +00:00
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#include "ARMGenRegisterInfo.inc"
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2009-07-08 17:28:55 +00:00
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2010-11-18 01:28:51 +00:00
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using namespace llvm;
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2009-07-08 18:31:39 +00:00
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ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
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2009-07-08 17:28:55 +00:00
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const ARMSubtarget &sti)
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2012-12-19 23:38:53 +00:00
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: ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti),
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2010-09-03 18:37:12 +00:00
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FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
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BasePtr(ARM::R6) {
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2009-07-08 17:28:55 +00:00
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}
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2012-03-04 03:33:22 +00:00
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const uint16_t*
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2009-07-08 17:28:55 +00:00
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ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2012-08-03 00:05:53 +00:00
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bool ghcCall = false;
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if (MF) {
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const Function *F = MF->getFunction();
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ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
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}
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if (ghcCall) {
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return CSR_GHC_SaveList;
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}
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else {
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2012-04-27 02:11:10 +00:00
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return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
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? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
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2012-08-03 00:05:53 +00:00
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}
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2012-01-17 23:09:00 +00:00
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}
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2009-07-08 17:28:55 +00:00
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2012-01-17 23:09:00 +00:00
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const uint32_t*
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ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
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2012-04-27 02:11:10 +00:00
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return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
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? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
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2009-07-08 17:28:55 +00:00
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}
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2012-11-06 23:05:24 +00:00
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const uint32_t*
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ARMBaseRegisterInfo::getNoPreservedMask() const {
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return CSR_NoRegs_RegMask;
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}
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2010-01-06 23:54:42 +00:00
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BitVector ARMBaseRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const {
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2011-01-10 12:39:04 +00:00
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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2010-11-18 21:19:35 +00:00
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2011-04-15 05:18:47 +00:00
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// FIXME: avoid re-calculating this every time.
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2009-07-08 17:28:55 +00:00
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BitVector Reserved(getNumRegs());
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Reserved.set(ARM::SP);
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Reserved.set(ARM::PC);
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2012-03-06 00:19:55 +00:00
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Reserved.set(ARM::FPSCR);
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2010-11-18 21:19:35 +00:00
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if (TFI->hasFP(MF))
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2009-07-08 17:28:55 +00:00
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Reserved.set(FramePtr);
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2010-09-03 18:37:12 +00:00
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if (hasBasePointer(MF))
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Reserved.set(BasePtr);
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2009-07-08 17:28:55 +00:00
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// Some targets reserve R9.
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if (STI.isR9Reserved())
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Reserved.set(ARM::R9);
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2011-06-18 00:53:27 +00:00
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// Reserve D16-D31 if the subtarget doesn't support them.
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if (!STI.hasVFP3() || STI.hasD16()) {
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assert(ARM::D31 == ARM::D16 + 15);
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for (unsigned i = 0; i != 16; ++i)
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Reserved.set(ARM::D16 + i);
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}
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2012-10-26 21:29:15 +00:00
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const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
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for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
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for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
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if (Reserved.test(*SI)) Reserved.set(*I);
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2009-07-08 17:28:55 +00:00
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return Reserved;
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}
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2011-04-26 18:52:33 +00:00
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const TargetRegisterClass*
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ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
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const {
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const TargetRegisterClass *Super = RC;
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2011-09-30 22:19:07 +00:00
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TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
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2011-04-26 18:52:33 +00:00
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do {
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switch (Super->getID()) {
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case ARM::GPRRegClassID:
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case ARM::SPRRegClassID:
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case ARM::DPRRegClassID:
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case ARM::QPRRegClassID:
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case ARM::QQPRRegClassID:
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case ARM::QQQQPRRegClassID:
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2012-10-26 21:29:15 +00:00
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case ARM::GPRPairRegClassID:
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2011-04-26 18:52:33 +00:00
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return Super;
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}
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Super = *I++;
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} while (Super);
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return RC;
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}
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Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 23:21:14 +00:00
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2009-07-29 20:31:52 +00:00
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const TargetRegisterClass *
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2012-05-07 22:10:26 +00:00
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ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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2012-04-20 07:30:17 +00:00
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return &ARM::GPRRegClass;
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2009-07-08 17:28:55 +00:00
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}
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2011-03-07 21:56:36 +00:00
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2011-08-30 01:34:54 +00:00
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const TargetRegisterClass *
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ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &ARM::CCRRegClass)
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return 0; // Can't copy CCR registers.
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return RC;
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}
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2011-03-07 21:56:36 +00:00
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unsigned
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ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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switch (RC->getID()) {
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default:
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return 0;
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case ARM::tGPRRegClassID:
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return TFI->hasFP(MF) ? 4 : 5;
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case ARM::GPRRegClassID: {
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unsigned FP = TFI->hasFP(MF) ? 1 : 0;
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return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
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}
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case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
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case ARM::DPRRegClassID:
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return 32 - 10;
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}
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}
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2009-07-08 17:28:55 +00:00
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2012-12-03 22:35:35 +00:00
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// Get the other register in a GPRPair.
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static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
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for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
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if (ARM::GPRPairRegClass.contains(*Supers))
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return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
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return 0;
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}
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// Resolve the RegPairEven / RegPairOdd register allocator hints.
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void
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ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const VirtRegMap *VRM) const {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
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unsigned Odd;
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switch (Hint.first) {
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case ARMRI::RegPairEven:
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Odd = 0;
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break;
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case ARMRI::RegPairOdd:
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Odd = 1;
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break;
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default:
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TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
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return;
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}
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// This register should preferably be even (Odd == 0) or odd (Odd == 1).
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// Check if the other part of the pair has already been assigned, and provide
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// the paired register as the first hint.
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unsigned PairedPhys = 0;
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if (VRM && VRM->hasPhys(Hint.second)) {
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PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
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if (PairedPhys && MRI.isReserved(PairedPhys))
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PairedPhys = 0;
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}
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// First prefer the paired physreg.
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if (PairedPhys)
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Hints.push_back(PairedPhys);
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// Then prefer even or odd registers.
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for (unsigned I = 0, E = Order.size(); I != E; ++I) {
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unsigned Reg = Order[I];
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if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
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continue;
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// Don't provide hints that are paired to a reserved register.
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unsigned Paired = getPairedGPR(Reg, !Odd, this);
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if (!Paired || MRI.isReserved(Paired))
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continue;
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Hints.push_back(Reg);
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}
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}
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2009-07-08 17:28:55 +00:00
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void
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ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const {
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
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if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
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Hint.first == (unsigned)ARMRI::RegPairEven) &&
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2011-01-10 02:58:51 +00:00
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TargetRegisterInfo::isVirtualRegister(Hint.second)) {
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2009-07-08 17:28:55 +00:00
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// If 'Reg' is one of the even / odd register pair and it's now changed
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// (e.g. coalesced) into a different register. The other register of the
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// pair allocation hint must be updated to reflect the relationship
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// change.
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unsigned OtherReg = Hint.second;
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Hint = MRI->getRegAllocationHint(OtherReg);
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if (Hint.second == Reg)
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// Make sure the pair has not already divorced.
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MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
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}
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}
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2011-04-19 18:11:45 +00:00
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bool
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ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
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// CortexA9 has a Write-after-write hazard for NEON registers.
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2012-09-13 15:05:10 +00:00
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if (!STI.isLikeA9())
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2011-04-19 18:11:45 +00:00
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return false;
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switch (RC->getID()) {
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case ARM::DPRRegClassID:
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case ARM::DPR_8RegClassID:
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case ARM::DPR_VFP2RegClassID:
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case ARM::QPRRegClassID:
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case ARM::QPR_8RegClassID:
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case ARM::QPR_VFP2RegClassID:
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case ARM::SPRRegClassID:
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case ARM::SPR_8RegClassID:
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// Avoid reusing S, D, and Q registers.
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// Don't increase register pressure for QQ and QQQQ.
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return true;
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default:
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return false;
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}
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}
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2009-07-08 17:28:55 +00:00
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2010-09-03 18:37:12 +00:00
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bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
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2010-09-03 15:26:42 +00:00
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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2010-09-02 22:29:01 +00:00
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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2012-02-28 01:15:01 +00:00
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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2010-09-03 18:37:12 +00:00
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2012-02-28 01:15:01 +00:00
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// When outgoing call frames are so large that we adjust the stack pointer
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// around the call, we can no longer use the stack pointer to reach the
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// emergency spill slot.
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2012-03-20 19:28:22 +00:00
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if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
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2010-09-03 18:37:12 +00:00
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return true;
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// Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
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// negative range for ldr/str (255), and thumb1 is positive offsets only.
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// It's going to be better to use the SP or Base Pointer instead. When there
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|
|
// are variable sized objects, we can't reference off of the SP, so we
|
|
|
|
// reserve a Base Pointer.
|
|
|
|
if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
|
|
|
|
// Conservatively estimate whether the negative offset from the frame
|
|
|
|
// pointer will be sufficient to reach. If a function has a smallish
|
|
|
|
// frame, it's less likely to have lots of spills and callee saved
|
|
|
|
// space, so it's all more likely to be within range of the frame pointer.
|
|
|
|
// If it's wrong, the scavenger will still enable access to work, it just
|
|
|
|
// won't be optimal.
|
|
|
|
if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
|
2012-01-05 00:26:52 +00:00
|
|
|
const MachineRegisterInfo *MRI = &MF.getRegInfo();
|
2011-10-20 00:07:12 +00:00
|
|
|
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
2010-09-08 17:22:12 +00:00
|
|
|
// We can't realign the stack if:
|
|
|
|
// 1. Dynamic stack realignment is explicitly disabled,
|
2011-10-20 00:07:12 +00:00
|
|
|
// 2. This is a Thumb1 function (it's not useful, so we don't bother), or
|
|
|
|
// 3. There are VLAs in the function and the base pointer is disabled.
|
2012-01-05 00:26:52 +00:00
|
|
|
if (!MF.getTarget().Options.RealignStack)
|
|
|
|
return false;
|
|
|
|
if (AFI->isThumb1OnlyFunction())
|
|
|
|
return false;
|
|
|
|
// Stack realignment requires a frame pointer. If we already started
|
|
|
|
// register allocation with frame pointer elimination, it is too late now.
|
|
|
|
if (!MRI->canReserveReg(FramePtr))
|
|
|
|
return false;
|
2012-03-20 19:28:25 +00:00
|
|
|
// We may also need a base pointer if there are dynamic allocas or stack
|
|
|
|
// pointer adjustments around calls.
|
|
|
|
if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
|
2012-01-05 00:26:52 +00:00
|
|
|
return true;
|
|
|
|
// A base pointer is required and allowed. Check that it isn't too late to
|
|
|
|
// reserve it.
|
|
|
|
return MRI->canReserveReg(BasePtr);
|
2010-01-19 18:31:11 +00:00
|
|
|
}
|
|
|
|
|
2009-10-27 22:45:39 +00:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
needsStackRealignment(const MachineFunction &MF) const {
|
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
2010-07-17 00:27:24 +00:00
|
|
|
const Function *F = MF.getFunction();
|
2011-01-10 12:39:04 +00:00
|
|
|
unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
|
2012-10-09 07:45:08 +00:00
|
|
|
bool requiresRealignment =
|
|
|
|
((MFI->getMaxAlignment() > StackAlign) ||
|
2012-12-19 07:18:57 +00:00
|
|
|
F->getFnAttributes().hasAttribute(Attribute::StackAlignment));
|
2010-09-02 19:52:39 +00:00
|
|
|
|
2010-07-17 00:27:24 +00:00
|
|
|
return requiresRealignment && canRealignStack(MF);
|
2009-10-27 22:45:39 +00:00
|
|
|
}
|
|
|
|
|
2010-01-06 23:54:42 +00:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
cannotEliminateFrame(const MachineFunction &MF) const {
|
2009-08-14 20:48:13 +00:00
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
2011-12-02 22:16:29 +00:00
|
|
|
if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
|
2009-08-14 20:48:13 +00:00
|
|
|
return true;
|
2009-11-08 00:27:19 +00:00
|
|
|
return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
|
|
|
|
|| needsStackRealignment(MF);
|
2009-08-14 20:48:13 +00:00
|
|
|
}
|
|
|
|
|
2010-09-02 19:52:39 +00:00
|
|
|
unsigned
|
2009-11-12 20:49:22 +00:00
|
|
|
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
2011-01-10 12:39:04 +00:00
|
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
2010-11-18 21:19:35 +00:00
|
|
|
|
|
|
|
if (TFI->hasFP(MF))
|
2009-07-08 17:28:55 +00:00
|
|
|
return FramePtr;
|
|
|
|
return ARM::SP;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("What is the exception register");
|
2009-07-08 17:28:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("What is the exception handler register");
|
2009-07-08 17:28:55 +00:00
|
|
|
}
|
|
|
|
|
2009-07-08 18:31:39 +00:00
|
|
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
|
|
/// specified immediate.
|
|
|
|
void ARMBaseRegisterInfo::
|
|
|
|
emitLoadConstPool(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MBBI,
|
2009-07-08 20:28:28 +00:00
|
|
|
DebugLoc dl,
|
2009-07-16 09:20:10 +00:00
|
|
|
unsigned DestReg, unsigned SubIdx, int Val,
|
2009-07-08 18:31:39 +00:00
|
|
|
ARMCC::CondCodes Pred,
|
2011-03-05 18:43:50 +00:00
|
|
|
unsigned PredReg, unsigned MIFlags) const {
|
2009-07-08 18:31:39 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
2010-04-15 01:51:59 +00:00
|
|
|
const Constant *C =
|
2009-08-13 21:58:54 +00:00
|
|
|
ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
|
2009-07-08 18:31:39 +00:00
|
|
|
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
|
|
|
|
|
2009-07-16 09:20:10 +00:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
|
|
|
|
.addReg(DestReg, getDefRegState(true), SubIdx)
|
2009-07-08 18:31:39 +00:00
|
|
|
.addConstantPoolIndex(Idx)
|
2011-03-05 18:43:50 +00:00
|
|
|
.addImm(0).addImm(Pred).addReg(PredReg)
|
|
|
|
.setMIFlags(MIFlags);
|
2009-07-08 18:31:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
|
|
return true;
|
|
|
|
}
|
2009-10-21 23:40:56 +00:00
|
|
|
|
2012-04-23 21:39:35 +00:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-10-20 01:26:58 +00:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
requiresFrameIndexScavenging(const MachineFunction &MF) const {
|
2009-10-28 17:33:28 +00:00
|
|
|
return true;
|
2009-10-20 01:26:58 +00:00
|
|
|
}
|
2009-07-08 18:31:39 +00:00
|
|
|
|
2010-08-24 19:05:43 +00:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
requiresVirtualBaseRegisters(const MachineFunction &MF) const {
|
2012-12-11 23:31:12 +00:00
|
|
|
return true;
|
2010-08-24 19:05:43 +00:00
|
|
|
}
|
|
|
|
|
2009-07-08 18:31:39 +00:00
|
|
|
static void
|
2009-07-28 05:48:47 +00:00
|
|
|
emitSPUpdate(bool isARM,
|
|
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|
|
|
DebugLoc dl, const ARMBaseInstrInfo &TII,
|
2009-07-08 18:31:39 +00:00
|
|
|
int NumBytes,
|
|
|
|
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
|
2009-07-28 05:48:47 +00:00
|
|
|
if (isARM)
|
|
|
|
emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
|
|
|
|
Pred, PredReg, TII);
|
|
|
|
else
|
|
|
|
emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
|
|
|
|
Pred, PredReg, TII);
|
2009-07-08 18:31:39 +00:00
|
|
|
}
|
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
|
2009-07-08 18:31:39 +00:00
|
|
|
void ARMBaseRegisterInfo::
|
|
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const {
|
2011-01-10 12:39:04 +00:00
|
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
2010-11-18 21:19:35 +00:00
|
|
|
if (!TFI->hasReservedCallFrame(MF)) {
|
2009-07-08 18:31:39 +00:00
|
|
|
// If we have alloca, convert as follows:
|
|
|
|
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
|
|
|
|
// ADJCALLSTACKUP -> add, sp, sp, amount
|
|
|
|
MachineInstr *Old = I;
|
|
|
|
DebugLoc dl = Old->getDebugLoc();
|
|
|
|
unsigned Amount = Old->getOperand(0).getImm();
|
|
|
|
if (Amount != 0) {
|
|
|
|
// We need to keep the stack aligned properly. To do this, we round the
|
|
|
|
// amount of space needed for the outgoing arguments up to the next
|
|
|
|
// alignment boundary.
|
2011-01-10 12:39:04 +00:00
|
|
|
unsigned Align = TFI->getStackAlignment();
|
2009-07-08 18:31:39 +00:00
|
|
|
Amount = (Amount+Align-1)/Align*Align;
|
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
2010-02-23 17:16:27 +00:00
|
|
|
"This eliminateCallFramePseudoInstr does not support Thumb1!");
|
2009-07-28 05:48:47 +00:00
|
|
|
bool isARM = !AFI->isThumbFunction();
|
|
|
|
|
2009-07-08 18:31:39 +00:00
|
|
|
// Replace the pseudo instruction with a new instruction...
|
|
|
|
unsigned Opc = Old->getOpcode();
|
2010-02-22 22:47:46 +00:00
|
|
|
int PIdx = Old->findFirstPredOperandIdx();
|
|
|
|
ARMCC::CondCodes Pred = (PIdx == -1)
|
|
|
|
? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
|
2009-07-08 18:31:39 +00:00
|
|
|
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
|
|
|
|
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
|
|
|
|
unsigned PredReg = Old->getOperand(2).getReg();
|
2009-07-28 05:48:47 +00:00
|
|
|
emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
|
2009-07-08 18:31:39 +00:00
|
|
|
} else {
|
|
|
|
// Note: PredReg is operand 3 for ADJCALLSTACKUP.
|
|
|
|
unsigned PredReg = Old->getOperand(3).getReg();
|
|
|
|
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
2009-07-28 05:48:47 +00:00
|
|
|
emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
|
2009-07-08 18:31:39 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
MBB.erase(I);
|
|
|
|
}
|
|
|
|
|
2010-08-19 23:52:25 +00:00
|
|
|
int64_t ARMBaseRegisterInfo::
|
2010-08-26 21:56:30 +00:00
|
|
|
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &Desc = MI->getDesc();
|
2010-08-19 23:52:25 +00:00
|
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
2012-02-22 17:25:00 +00:00
|
|
|
int64_t InstrOffs = 0;
|
2010-08-19 23:52:25 +00:00
|
|
|
int Scale = 1;
|
|
|
|
unsigned ImmIdx = 0;
|
2010-08-26 21:56:30 +00:00
|
|
|
switch (AddrMode) {
|
2010-08-19 23:52:25 +00:00
|
|
|
case ARMII::AddrModeT2_i8:
|
|
|
|
case ARMII::AddrModeT2_i12:
|
2010-10-26 22:37:02 +00:00
|
|
|
case ARMII::AddrMode_i12:
|
2010-08-19 23:52:25 +00:00
|
|
|
InstrOffs = MI->getOperand(Idx+1).getImm();
|
|
|
|
Scale = 1;
|
|
|
|
break;
|
|
|
|
case ARMII::AddrMode5: {
|
|
|
|
// VFP address mode.
|
|
|
|
const MachineOperand &OffOp = MI->getOperand(Idx+1);
|
2010-08-25 19:11:34 +00:00
|
|
|
InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
|
2010-08-19 23:52:25 +00:00
|
|
|
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
|
|
|
|
InstrOffs = -InstrOffs;
|
|
|
|
Scale = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ARMII::AddrMode2: {
|
|
|
|
ImmIdx = Idx+2;
|
|
|
|
InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
|
|
|
|
if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
|
|
InstrOffs = -InstrOffs;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ARMII::AddrMode3: {
|
|
|
|
ImmIdx = Idx+2;
|
|
|
|
InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
|
|
|
|
if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
|
|
InstrOffs = -InstrOffs;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ARMII::AddrModeT1_s: {
|
|
|
|
ImmIdx = Idx+1;
|
|
|
|
InstrOffs = MI->getOperand(ImmIdx).getImm();
|
|
|
|
Scale = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
|
|
}
|
|
|
|
|
|
|
|
return InstrOffs * Scale;
|
|
|
|
}
|
|
|
|
|
2010-08-17 18:13:53 +00:00
|
|
|
/// needsFrameBaseReg - Returns true if the instruction's frame index
|
|
|
|
/// reference would be better served by a base register other than FP
|
|
|
|
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
|
|
|
|
/// references it should create new base registers for.
|
|
|
|
bool ARMBaseRegisterInfo::
|
2010-08-24 21:19:33 +00:00
|
|
|
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
|
|
|
|
for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
|
|
|
|
assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
2010-08-17 18:13:53 +00:00
|
|
|
|
|
|
|
// It's the load/store FI references that cause issues, as it can be difficult
|
|
|
|
// to materialize the offset if it won't fit in the literal field. Estimate
|
|
|
|
// based on the size of the local frame and some conservative assumptions
|
|
|
|
// about the rest of the stack frame (note, this is pre-regalloc, so
|
|
|
|
// we don't know everything for certain yet) whether this offset is likely
|
|
|
|
// to be out of range of the immediate. Return true if so.
|
|
|
|
|
2010-08-24 18:04:52 +00:00
|
|
|
// We only generate virtual base registers for loads and stores, so
|
|
|
|
// return false for everything else.
|
2010-08-17 18:13:53 +00:00
|
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
switch (Opc) {
|
2012-08-28 03:11:27 +00:00
|
|
|
case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
|
2010-10-27 23:12:14 +00:00
|
|
|
case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
|
2012-08-28 03:11:27 +00:00
|
|
|
case ARM::t2LDRi12: case ARM::t2LDRi8:
|
|
|
|
case ARM::t2STRi12: case ARM::t2STRi8:
|
2010-08-17 18:13:53 +00:00
|
|
|
case ARM::VLDRS: case ARM::VLDRD:
|
|
|
|
case ARM::VSTRS: case ARM::VSTRD:
|
2010-08-19 17:52:13 +00:00
|
|
|
case ARM::tSTRspi: case ARM::tLDRspi:
|
2010-08-24 18:04:52 +00:00
|
|
|
break;
|
2010-08-17 18:13:53 +00:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2010-08-24 18:04:52 +00:00
|
|
|
|
|
|
|
// Without a virtual base register, if the function has variable sized
|
|
|
|
// objects, all fixed-size local references will be via the frame pointer,
|
2010-08-24 21:19:33 +00:00
|
|
|
// Approximate the offset and see if it's legal for the instruction.
|
|
|
|
// Note that the incoming offset is based on the SP value at function entry,
|
|
|
|
// so it'll be negative.
|
|
|
|
MachineFunction &MF = *MI->getParent()->getParent();
|
2011-01-10 12:39:04 +00:00
|
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
2010-08-24 21:19:33 +00:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
|
|
|
|
// Estimate an offset from the frame pointer.
|
|
|
|
// Conservatively assume all callee-saved registers get pushed. R4-R6
|
|
|
|
// will be earlier than the FP, so we ignore those.
|
|
|
|
// R7, LR
|
|
|
|
int64_t FPOffset = Offset - 8;
|
|
|
|
// ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
|
|
|
|
if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
|
|
|
|
FPOffset -= 80;
|
|
|
|
// Estimate an offset from the stack pointer.
|
2010-08-31 18:52:31 +00:00
|
|
|
// The incoming offset is relating to the SP at the start of the function,
|
|
|
|
// but when we access the local it'll be relative to the SP after local
|
|
|
|
// allocation, so adjust our SP-relative offset by that allocation size.
|
2010-08-24 21:19:33 +00:00
|
|
|
Offset = -Offset;
|
2010-08-31 18:52:31 +00:00
|
|
|
Offset += MFI->getLocalFrameSize();
|
2010-08-24 21:19:33 +00:00
|
|
|
// Assume that we'll have at least some spill slots allocated.
|
|
|
|
// FIXME: This is a total SWAG number. We should run some statistics
|
|
|
|
// and pick a real one.
|
|
|
|
Offset += 128; // 128 bytes of spill slots
|
|
|
|
|
|
|
|
// If there is a frame pointer, try using it.
|
|
|
|
// The FP is only available if there is no dynamic realignment. We
|
|
|
|
// don't know for sure yet whether we'll need that, so we guess based
|
|
|
|
// on whether there are any local variables that would trigger it.
|
2011-01-10 12:39:04 +00:00
|
|
|
unsigned StackAlign = TFI->getStackAlignment();
|
2010-11-18 21:19:35 +00:00
|
|
|
if (TFI->hasFP(MF) &&
|
2010-08-24 21:19:33 +00:00
|
|
|
!((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
|
|
|
|
if (isFrameOffsetLegal(MI, FPOffset))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// If we can reference via the stack pointer, try that.
|
|
|
|
// FIXME: This (and the code that resolves the references) can be improved
|
|
|
|
// to only disallow SP relative references in the live range of
|
|
|
|
// the VLA(s). In practice, it's unclear how much difference that
|
|
|
|
// would make, but it may be worth doing.
|
|
|
|
if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
|
|
|
|
return false;
|
2010-08-24 18:04:52 +00:00
|
|
|
|
2010-08-24 21:19:33 +00:00
|
|
|
// The offset likely isn't legal, we want to allocate a virtual base register.
|
2010-08-24 18:04:52 +00:00
|
|
|
return true;
|
2010-08-17 18:13:53 +00:00
|
|
|
}
|
|
|
|
|
2010-12-17 23:09:14 +00:00
|
|
|
/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
|
|
|
|
/// be a pointer to FrameIdx at the beginning of the basic block.
|
2010-08-17 22:41:55 +00:00
|
|
|
void ARMBaseRegisterInfo::
|
2010-12-17 23:09:14 +00:00
|
|
|
materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
|
|
|
unsigned BaseReg, int FrameIdx,
|
|
|
|
int64_t Offset) const {
|
|
|
|
ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
|
2010-08-19 17:52:13 +00:00
|
|
|
unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
|
|
|
|
(AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
|
2010-08-17 22:41:55 +00:00
|
|
|
|
2010-12-17 23:09:14 +00:00
|
|
|
MachineBasicBlock::iterator Ins = MBB->begin();
|
|
|
|
DebugLoc DL; // Defaults to "unknown"
|
|
|
|
if (Ins != MBB->end())
|
|
|
|
DL = Ins->getDebugLoc();
|
|
|
|
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &MCID = TII.get(ADDriOpc);
|
2011-05-19 02:18:27 +00:00
|
|
|
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
2012-05-07 22:10:26 +00:00
|
|
|
const MachineFunction &MF = *MBB->getParent();
|
|
|
|
MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
|
2011-05-19 02:18:27 +00:00
|
|
|
|
2011-08-24 17:46:13 +00:00
|
|
|
MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
|
|
|
.addFrameIndex(FrameIdx).addImm(Offset));
|
2010-12-17 23:09:14 +00:00
|
|
|
|
2010-08-19 17:52:13 +00:00
|
|
|
if (!AFI->isThumb1OnlyFunction())
|
2011-08-24 17:46:13 +00:00
|
|
|
AddDefaultCC(MIB);
|
2010-08-17 22:41:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
|
|
|
|
unsigned BaseReg, int64_t Offset) const {
|
|
|
|
MachineInstr &MI = *I;
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
int Off = Offset; // ARM doesn't need the general 64-bit offsets
|
|
|
|
unsigned i = 0;
|
|
|
|
|
|
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
|
|
|
"This resolveFrameIndex does not support Thumb1!");
|
|
|
|
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
|
|
++i;
|
|
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
|
|
|
bool Done = false;
|
|
|
|
if (!AFI->isThumbFunction())
|
|
|
|
Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
|
|
|
|
else {
|
|
|
|
assert(AFI->isThumb2Function());
|
|
|
|
Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
|
|
|
|
}
|
|
|
|
assert (Done && "Unable to resolve frame index!");
|
2011-08-12 14:54:45 +00:00
|
|
|
(void)Done;
|
2010-08-17 22:41:55 +00:00
|
|
|
}
|
2010-08-17 18:13:53 +00:00
|
|
|
|
2010-08-19 23:52:25 +00:00
|
|
|
bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
|
|
|
|
int64_t Offset) const {
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &Desc = MI->getDesc();
|
2010-08-18 22:44:49 +00:00
|
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
|
|
unsigned i = 0;
|
|
|
|
|
|
|
|
while (!MI->getOperand(i).isFI()) {
|
|
|
|
++i;
|
|
|
|
assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
|
|
|
|
|
|
|
// AddrMode4 and AddrMode6 cannot handle any offset.
|
|
|
|
if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
|
|
|
|
return Offset == 0;
|
|
|
|
|
|
|
|
unsigned NumBits = 0;
|
|
|
|
unsigned Scale = 1;
|
2010-08-19 23:52:25 +00:00
|
|
|
bool isSigned = true;
|
2010-08-26 21:56:30 +00:00
|
|
|
switch (AddrMode) {
|
2010-08-18 22:44:49 +00:00
|
|
|
case ARMII::AddrModeT2_i8:
|
|
|
|
case ARMII::AddrModeT2_i12:
|
|
|
|
// i8 supports only negative, and i12 supports only positive, so
|
|
|
|
// based on Offset sign, consider the appropriate instruction
|
2010-08-19 17:52:13 +00:00
|
|
|
Scale = 1;
|
2010-08-18 22:44:49 +00:00
|
|
|
if (Offset < 0) {
|
|
|
|
NumBits = 8;
|
|
|
|
Offset = -Offset;
|
|
|
|
} else {
|
|
|
|
NumBits = 12;
|
|
|
|
}
|
|
|
|
break;
|
2010-08-26 21:56:30 +00:00
|
|
|
case ARMII::AddrMode5:
|
2010-08-18 22:44:49 +00:00
|
|
|
// VFP address mode.
|
|
|
|
NumBits = 8;
|
|
|
|
Scale = 4;
|
|
|
|
break;
|
2010-10-26 22:37:02 +00:00
|
|
|
case ARMII::AddrMode_i12:
|
2010-08-26 21:56:30 +00:00
|
|
|
case ARMII::AddrMode2:
|
2010-08-18 22:44:49 +00:00
|
|
|
NumBits = 12;
|
|
|
|
break;
|
2010-08-26 21:56:30 +00:00
|
|
|
case ARMII::AddrMode3:
|
2010-08-18 22:44:49 +00:00
|
|
|
NumBits = 8;
|
|
|
|
break;
|
2011-10-11 21:40:47 +00:00
|
|
|
case ARMII::AddrModeT1_s:
|
|
|
|
NumBits = 5;
|
2010-08-19 17:52:13 +00:00
|
|
|
Scale = 4;
|
2010-08-19 23:52:25 +00:00
|
|
|
isSigned = false;
|
2010-08-19 17:52:13 +00:00
|
|
|
break;
|
2010-08-18 22:44:49 +00:00
|
|
|
default:
|
|
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
|
|
}
|
|
|
|
|
2010-08-26 21:56:30 +00:00
|
|
|
Offset += getFrameIndexInstrOffset(MI, i);
|
2010-08-31 18:49:31 +00:00
|
|
|
// Make sure the offset is encodable for instructions that scale the
|
|
|
|
// immediate.
|
|
|
|
if ((Offset & (Scale-1)) != 0)
|
|
|
|
return false;
|
|
|
|
|
2010-08-19 23:52:25 +00:00
|
|
|
if (isSigned && Offset < 0)
|
2010-08-18 22:44:49 +00:00
|
|
|
Offset = -Offset;
|
|
|
|
|
|
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
|
|
if ((unsigned)Offset <= Mask * Scale)
|
|
|
|
return true;
|
2010-08-18 17:57:37 +00:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-08-26 23:32:16 +00:00
|
|
|
void
|
2009-07-28 05:48:47 +00:00
|
|
|
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
2010-08-26 23:32:16 +00:00
|
|
|
int SPAdj, RegScavenger *RS) const {
|
2009-07-24 00:16:18 +00:00
|
|
|
unsigned i = 0;
|
|
|
|
MachineInstr &MI = *II;
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2011-01-10 12:39:04 +00:00
|
|
|
const ARMFrameLowering *TFI =
|
|
|
|
static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
|
2009-07-24 00:16:18 +00:00
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
2009-07-28 05:48:47 +00:00
|
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
2009-09-18 21:42:44 +00:00
|
|
|
"This eliminateFrameIndex does not support Thumb1!");
|
2009-07-24 00:16:18 +00:00
|
|
|
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
|
|
++i;
|
|
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
|
|
|
|
|
|
|
int FrameIndex = MI.getOperand(i).getIndex();
|
2009-11-22 20:05:32 +00:00
|
|
|
unsigned FrameReg;
|
2009-07-24 00:16:18 +00:00
|
|
|
|
2010-11-20 15:59:32 +00:00
|
|
|
int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
|
2009-07-24 00:16:18 +00:00
|
|
|
|
2012-02-28 01:15:01 +00:00
|
|
|
// PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
|
|
|
|
// call frame setup/destroy instructions have already been eliminated. That
|
|
|
|
// means the stack pointer cannot be used to access the emergency spill slot
|
|
|
|
// when !hasReservedCallFrame().
|
|
|
|
#ifndef NDEBUG
|
|
|
|
if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
|
|
|
|
assert(TFI->hasReservedCallFrame(MF) &&
|
|
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
|
|
"functions without a reserved call frame");
|
|
|
|
assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
|
|
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
|
|
"functions with variable sized frame objects");
|
|
|
|
}
|
|
|
|
#endif // NDEBUG
|
|
|
|
|
2010-04-26 07:39:25 +00:00
|
|
|
// Special handling of dbg_value instructions.
|
|
|
|
if (MI.isDebugValue()) {
|
|
|
|
MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
|
|
|
|
MI.getOperand(i+1).ChangeToImmediate(Offset);
|
2010-08-26 23:32:16 +00:00
|
|
|
return;
|
2010-04-26 07:39:25 +00:00
|
|
|
}
|
|
|
|
|
2009-11-01 21:12:51 +00:00
|
|
|
// Modify MI as necessary to handle as much of 'Offset' as possible
|
2009-08-27 01:23:50 +00:00
|
|
|
bool Done = false;
|
2009-07-28 05:48:47 +00:00
|
|
|
if (!AFI->isThumbFunction())
|
2009-08-27 01:23:50 +00:00
|
|
|
Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
|
2009-07-28 05:48:47 +00:00
|
|
|
else {
|
|
|
|
assert(AFI->isThumb2Function());
|
2009-08-27 01:23:50 +00:00
|
|
|
Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
2009-08-27 01:23:50 +00:00
|
|
|
if (Done)
|
2010-08-26 23:32:16 +00:00
|
|
|
return;
|
2009-07-24 00:16:18 +00:00
|
|
|
|
2009-07-08 18:31:39 +00:00
|
|
|
// If we get here, the immediate doesn't fit into the instruction. We folded
|
|
|
|
// as much as possible above, handle the rest, providing a register that is
|
|
|
|
// SP+LargeImm.
|
2009-08-28 08:08:22 +00:00
|
|
|
assert((Offset ||
|
2009-11-15 21:45:34 +00:00
|
|
|
(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
|
|
|
|
(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
|
2009-08-27 01:23:50 +00:00
|
|
|
"This code isn't needed if offset already handled!");
|
2009-07-08 18:31:39 +00:00
|
|
|
|
2009-10-20 01:26:58 +00:00
|
|
|
unsigned ScratchReg = 0;
|
2009-07-08 18:31:39 +00:00
|
|
|
int PIdx = MI.findFirstPredOperandIdx();
|
|
|
|
ARMCC::CondCodes Pred = (PIdx == -1)
|
|
|
|
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
|
|
|
|
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
|
2009-08-27 01:23:50 +00:00
|
|
|
if (Offset == 0)
|
2009-11-15 21:45:34 +00:00
|
|
|
// Must be addrmode4/6.
|
2009-08-27 01:23:50 +00:00
|
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
|
2009-07-28 05:48:47 +00:00
|
|
|
else {
|
2012-04-20 07:30:17 +00:00
|
|
|
ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
|
2009-08-27 01:23:50 +00:00
|
|
|
if (!AFI->isThumbFunction())
|
|
|
|
emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
|
|
|
Offset, Pred, PredReg, TII);
|
|
|
|
else {
|
|
|
|
assert(AFI->isThumb2Function());
|
|
|
|
emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
|
|
|
Offset, Pred, PredReg, TII);
|
|
|
|
}
|
2010-12-09 01:22:13 +00:00
|
|
|
// Update the original instruction to use the scratch register.
|
2009-08-27 01:23:50 +00:00
|
|
|
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
2009-07-08 18:31:39 +00:00
|
|
|
}
|