llvm-6502/test/CodeGen/R600/si-annotate-cf-assertion.ll

; REQUIRES: asserts
; XFAIL: *
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs-asm-verbose=false < %s | FileCheck %s


define void @test(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
; CHECK-LABEL: @test:

entry:
  switch i32 %x, label %sw.default [
    i32 0, label %sw.bb
    i32 60, label %sw.bb
  ]

sw.bb:
  unreachable

sw.default:
  unreachable

sw.epilog:
  ret void
}
Add REQUIRES:asserts to 3 tests in llvm/test/CodeGen/R600 added in r192212. They are failing in assertions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197669 91177308-0d34-0410-b5e6-96231b3b80d8 2013-12-19 10:41:12 +00:00			`; REQUIRES: asserts`
Add some xfaild R600 tests. These are bugs to fix later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192212 91177308-0d34-0410-b5e6-96231b3b80d8 2013-10-08 18:06:36 +00:00			`; XFAIL: *`
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF\|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207591 91177308-0d34-0410-b5e6-96231b3b80d8 2014-04-29 23:12:53 +00:00			`; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs-asm-verbose=false < %s \| FileCheck %s`
Add some xfaild R600 tests. These are bugs to fix later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192212 91177308-0d34-0410-b5e6-96231b3b80d8 2013-10-08 18:06:36 +00:00

			`define void @test(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {`
			`; CHECK-LABEL: @test:`

			`entry:`
			`switch i32 %x, label %sw.default [`
			`i32 0, label %sw.bb`
			`i32 60, label %sw.bb`
			`]`

			`sw.bb:`
			`unreachable`

			`sw.default:`
			`unreachable`

			`sw.epilog:`
			`ret void`
			`}`