2012-02-28 07:46:26 +00:00
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//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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2011-07-01 21:01:15 +00:00
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// This file declares the Mips specific subclass of TargetSubtargetInfo.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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#ifndef MIPSSUBTARGET_H
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#define MIPSSUBTARGET_H
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2011-06-29 01:14:12 +00:00
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#include "llvm/MC/MCInstrItineraries.h"
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2013-04-09 19:46:01 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2012-12-04 07:12:27 +00:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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2007-06-06 07:42:06 +00:00
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#include <string>
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2011-07-01 20:45:01 +00:00
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#define GET_SUBTARGETINFO_HEADER
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2011-07-01 22:36:09 +00:00
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#include "MipsGenSubtargetInfo.inc"
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2011-07-01 20:45:01 +00:00
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2007-06-06 07:42:06 +00:00
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namespace llvm {
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2011-07-07 07:07:08 +00:00
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class StringRef;
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2007-06-06 07:42:06 +00:00
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2013-04-09 19:46:01 +00:00
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class MipsTargetMachine;
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2011-07-01 20:45:01 +00:00
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class MipsSubtarget : public MipsGenSubtargetInfo {
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2011-12-20 02:50:00 +00:00
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virtual void anchor();
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2007-08-18 01:52:27 +00:00
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2008-07-14 14:42:54 +00:00
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public:
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2011-09-14 17:22:51 +00:00
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// NOTE: O64 will not be supported.
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2008-07-14 14:42:54 +00:00
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enum MipsABIEnum {
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2011-09-21 02:45:29 +00:00
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UnknownABI, O32, N32, N64, EABI
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2011-03-04 17:51:39 +00:00
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};
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2008-07-14 14:42:54 +00:00
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2007-06-06 07:42:06 +00:00
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protected:
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2014-04-03 12:13:36 +00:00
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enum MipsArchEnum { Mips32, Mips32r2, Mips4, Mips64, Mips64r2 };
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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2011-03-04 17:51:39 +00:00
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// Mips architecture version
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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MipsArchEnum MipsArchVersion;
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2011-03-04 17:51:39 +00:00
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// Mips supported ABIs
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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MipsABIEnum MipsABI;
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// IsLittle - The target is Little Endian
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2008-06-04 01:45:25 +00:00
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bool IsLittle;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// IsSingleFloat - The target only supports single precision float
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// point operations. This enable the target to use all 32 32-bit
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2008-07-09 04:45:36 +00:00
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// floating point registers instead of only using even ones.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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bool IsSingleFloat;
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2008-07-09 04:45:36 +00:00
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// IsFP64bit - The target processor has 64-bit floating point registers.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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bool IsFP64bit;
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// IsFP64bit - General-purpose registers are 64 bits wide
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bool IsGP64bit;
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2008-07-09 05:32:22 +00:00
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// HasVFPU - Processor has a vector floating point unit.
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bool HasVFPU;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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2014-03-20 11:51:58 +00:00
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// CPU supports cnMIPS (Cavium Networks Octeon CPU).
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bool HasCnMips;
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2008-07-14 14:42:54 +00:00
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// isLinux - Target system is Linux. Is false we consider ELFOS for now.
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bool IsLinux;
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2012-08-22 03:18:13 +00:00
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// UseSmallSection - Small section is used.
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bool UseSmallSection;
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2008-07-30 17:01:06 +00:00
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/// Features related to the presence of specific instructions.
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2011-03-04 17:51:39 +00:00
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2008-07-30 17:01:06 +00:00
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// HasSEInReg - SEB and SEH (signext in register) instructions.
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bool HasSEInReg;
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// HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
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bool HasCondMov;
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// HasSwap - Byte and half swap instructions.
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bool HasSwap;
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// HasBitCount - Count leading '1' and '0' bits.
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bool HasBitCount;
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2012-11-15 21:17:13 +00:00
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// HasFPIdx -- Floating point indexed load/store instructions.
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bool HasFPIdx;
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2012-05-16 22:19:56 +00:00
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// InMips16 -- can process Mips16 instructions
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bool InMips16Mode;
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Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
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// Mips16 hard float
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bool InMips16HardFloat;
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2013-04-09 19:46:01 +00:00
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// PreviousInMips16 -- the function we just processed was in Mips 16 Mode
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bool PreviousInMips16Mode;
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2013-02-05 09:30:03 +00:00
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// InMicroMips -- can process MicroMips instructions
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bool InMicroMipsMode;
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2012-09-21 23:41:49 +00:00
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// HasDSP, HasDSPR2 -- supports DSP ASE.
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bool HasDSP, HasDSPR2;
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2013-04-09 19:46:01 +00:00
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// Allow mixed Mips16 and Mips32 in one source file
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bool AllowMixed16_32;
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2013-04-10 16:58:04 +00:00
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// Optimize for space by compiling all functions as Mips 16 unless
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// it needs floating point. Functions needing floating point are
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// compiled as Mips32
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bool Os16;
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2013-08-13 20:54:07 +00:00
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// HasMSA -- supports MSA ASE.
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bool HasMSA;
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2007-08-18 01:52:27 +00:00
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InstrItineraryData InstrItins;
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2013-01-30 02:16:36 +00:00
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// Relocation Model
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Reloc::Model RM;
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2013-04-09 19:46:01 +00:00
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// We can override the determination of whether we are in mips16 mode
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// as from the command line
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enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
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MipsTargetMachine *TM;
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2014-02-05 17:19:30 +00:00
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Triple TargetTriple;
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2007-06-06 07:42:06 +00:00
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public:
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2012-03-28 00:24:17 +00:00
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virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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/// Only O32 and EABI supported right now.
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bool isABI_EABI() const { return MipsABI == EABI; }
|
2011-09-20 20:28:08 +00:00
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bool isABI_N64() const { return MipsABI == N64; }
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|
|
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bool isABI_N32() const { return MipsABI == N32; }
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
bool isABI_O32() const { return MipsABI == O32; }
|
2008-07-14 14:42:54 +00:00
|
|
|
unsigned getTargetABI() const { return MipsABI; }
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
/// This constructor initializes the data members to match that
|
2009-08-02 22:11:08 +00:00
|
|
|
/// of the specified triple.
|
2011-06-30 01:53:36 +00:00
|
|
|
MipsSubtarget(const std::string &TT, const std::string &CPU,
|
2013-04-09 19:46:01 +00:00
|
|
|
const std::string &FS, bool little, Reloc::Model RM,
|
|
|
|
MipsTargetMachine *TM);
|
2011-03-04 17:51:39 +00:00
|
|
|
|
|
|
|
/// ParseSubtargetFeatures - Parses features string setting specified
|
2007-06-06 07:42:06 +00:00
|
|
|
/// subtarget options. Definition of function is auto generated by tblgen.
|
2011-07-07 07:07:08 +00:00
|
|
|
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2011-09-20 23:53:09 +00:00
|
|
|
bool hasMips32() const { return MipsArchVersion >= Mips32; }
|
|
|
|
bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
|
2011-09-20 20:28:08 +00:00
|
|
|
MipsArchVersion == Mips64r2; }
|
2011-09-21 02:24:25 +00:00
|
|
|
bool hasMips64() const { return MipsArchVersion >= Mips64; }
|
|
|
|
bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
|
2008-06-04 01:45:25 +00:00
|
|
|
|
2014-03-20 11:51:58 +00:00
|
|
|
bool hasCnMips() const { return HasCnMips; }
|
|
|
|
|
2008-06-04 01:45:25 +00:00
|
|
|
bool isLittle() const { return IsLittle; }
|
2009-12-19 07:05:23 +00:00
|
|
|
bool isFP64bit() const { return IsFP64bit; }
|
2013-08-20 23:38:40 +00:00
|
|
|
bool isNotFP64bit() const { return !IsFP64bit; }
|
2009-12-19 07:05:23 +00:00
|
|
|
bool isGP64bit() const { return IsGP64bit; }
|
|
|
|
bool isGP32bit() const { return !IsGP64bit; }
|
|
|
|
bool isSingleFloat() const { return IsSingleFloat; }
|
|
|
|
bool isNotSingleFloat() const { return !IsSingleFloat; }
|
|
|
|
bool hasVFPU() const { return HasVFPU; }
|
2013-04-09 19:46:01 +00:00
|
|
|
bool inMips16Mode() const {
|
|
|
|
switch (OverrideMode) {
|
|
|
|
case NoOverride:
|
|
|
|
return InMips16Mode;
|
|
|
|
case Mips16Override:
|
|
|
|
return true;
|
|
|
|
case NoMips16Override:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
llvm_unreachable("Unexpected mode");
|
|
|
|
}
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
bool inMips16ModeDefault() const {
|
2013-04-09 19:46:01 +00:00
|
|
|
return InMips16Mode;
|
|
|
|
}
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
bool inMips16HardFloat() const {
|
|
|
|
return inMips16Mode() && InMips16HardFloat;
|
|
|
|
}
|
2013-02-05 09:30:03 +00:00
|
|
|
bool inMicroMipsMode() const { return InMicroMipsMode; }
|
2012-09-21 23:41:49 +00:00
|
|
|
bool hasDSP() const { return HasDSP; }
|
|
|
|
bool hasDSPR2() const { return HasDSPR2; }
|
2013-08-13 20:54:07 +00:00
|
|
|
bool hasMSA() const { return HasMSA; }
|
2009-12-19 07:05:23 +00:00
|
|
|
bool isLinux() const { return IsLinux; }
|
2012-08-22 03:18:13 +00:00
|
|
|
bool useSmallSection() const { return UseSmallSection; }
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
2012-05-22 03:10:09 +00:00
|
|
|
bool hasStandardEncoding() const { return !inMips16Mode(); }
|
|
|
|
|
2013-08-30 19:40:56 +00:00
|
|
|
bool mipsSEUsesSoftFloat() const;
|
|
|
|
|
2013-10-07 19:06:57 +00:00
|
|
|
bool enableLongBranchPass() const {
|
|
|
|
return hasStandardEncoding() || allowMixed16_32();
|
|
|
|
}
|
|
|
|
|
2008-07-30 17:01:06 +00:00
|
|
|
/// Features related to the presence of specific instructions.
|
2009-12-19 07:05:23 +00:00
|
|
|
bool hasSEInReg() const { return HasSEInReg; }
|
|
|
|
bool hasCondMov() const { return HasCondMov; }
|
|
|
|
bool hasSwap() const { return HasSwap; }
|
|
|
|
bool hasBitCount() const { return HasBitCount; }
|
2012-11-15 21:17:13 +00:00
|
|
|
bool hasFPIdx() const { return HasFPIdx; }
|
2013-10-09 23:36:17 +00:00
|
|
|
bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
|
2013-01-18 21:20:38 +00:00
|
|
|
|
2013-07-12 23:33:22 +00:00
|
|
|
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
|
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10 22:25:39 +00:00
|
|
|
bool allowMixed16_32() const { return inMips16ModeDefault() |
|
|
|
|
AllowMixed16_32;}
|
2013-04-09 19:46:01 +00:00
|
|
|
|
2013-04-10 16:58:04 +00:00
|
|
|
bool os16() const { return Os16;};
|
|
|
|
|
2014-02-05 17:19:30 +00:00
|
|
|
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
|
2014-02-07 17:16:40 +00:00
|
|
|
bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
|
2014-02-05 17:19:30 +00:00
|
|
|
|
2013-10-27 21:57:36 +00:00
|
|
|
// for now constant islands are on for the whole compilation unit but we only
|
|
|
|
// really use them if in addition we are in mips16 mode
|
|
|
|
//
|
|
|
|
static bool useConstantIslands();
|
2013-10-29 19:29:03 +00:00
|
|
|
|
2013-11-11 21:49:03 +00:00
|
|
|
unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
|
2013-10-29 19:29:03 +00:00
|
|
|
|
2013-01-30 02:16:36 +00:00
|
|
|
// Grab relocation model
|
|
|
|
Reloc::Model getRelocationModel() const {return RM;}
|
2013-04-09 19:46:01 +00:00
|
|
|
|
|
|
|
/// \brief Reset the subtarget for the Mips target.
|
|
|
|
void resetSubtarget(MachineFunction *MF);
|
|
|
|
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
|
|
|
|
#endif
|