llvm-6502/lib/Target/ARM/ARMScheduleV6.td

//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
// 
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// 
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the ARM v6 processors.
//
//===----------------------------------------------------------------------===//

// TODO: Add model for an ARM11
Fix comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76693 91177308-0d34-0410-b5e6-96231b3b80d8 2009-07-21 23:54:22 +00:00			`//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----- tablegen --===//`
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-19 01:51:50 +00:00			`//`
			`// The LLVM Compiler Infrastructure`
			`//`
			`// This file is distributed under the University of Illinois Open Source`
			`// License. See LICENSE.TXT for details.`
			`//`
			`//===----------------------------------------------------------------------===//`
			`//`
			`// This file defines the itinerary class data for the ARM v6 processors.`
			`//`
			`//===----------------------------------------------------------------------===//`

Checkpoint NEON scheduling itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-23 21:38:08 +00:00			`// TODO: Add model for an ARM11`