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https://github.com/c64scene-ar/llvm-6502.git
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97 lines
2.9 KiB
LLVM
97 lines
2.9 KiB
LLVM
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vceq\\.f32} %t | count 1
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; RUN: grep {vcgt\\.f32} %t | count 9
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; RUN: grep {vcge\\.f32} %t | count 5
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; RUN: grep vorr %t | count 4
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; RUN: grep vmvn %t | count 7
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; This tests vfcmp operations that do not map directly to NEON instructions.
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; une is implemented with VCEQ/VMVN
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define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp une <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; olt is implemented with VCGT
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define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp olt <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; ole is implemented with VCGE
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define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp ole <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; uge is implemented with VCGT/VMVN
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define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp uge <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; ule is implemented with VCGT/VMVN
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define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp ule <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; ugt is implemented with VCGE/VMVN
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define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp ugt <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; ult is implemented with VCGE/VMVN
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define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp ult <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; ueq is implemented with VCGT/VCGT/VORR/VMVN
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define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp ueq <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; one is implemented with VCGT/VCGT/VORR
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define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp one <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; uno is implemented with VCGT/VCGE/VORR/VMVN
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define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp uno <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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; ord is implemented with VCGT/VCGE/VORR
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define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp ord <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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