2011-12-22 01:57:09 +00:00
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//===-- PPCELFObjectWriter.cpp - PPC ELF Writer ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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2012-12-03 16:50:05 +00:00
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#include "MCTargetDesc/PPCFixupKinds.h"
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2012-12-14 20:28:38 +00:00
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#include "llvm/ADT/STLExtras.h"
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2011-12-22 01:57:09 +00:00
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#include "llvm/MC/MCELFObjectWriter.h"
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2012-10-25 12:27:42 +00:00
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCValue.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2011-12-22 01:57:09 +00:00
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using namespace llvm;
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namespace {
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class PPCELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI);
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virtual ~PPCELFObjectWriter();
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protected:
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2012-10-25 12:27:42 +00:00
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virtual unsigned getRelocTypeInner(const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const;
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2011-12-22 01:57:09 +00:00
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virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
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bool IsPCRel, bool IsRelocWithSymbol,
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int64_t Addend) const;
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2012-10-25 12:27:42 +00:00
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virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const;
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2011-12-22 01:57:09 +00:00
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virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset);
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2012-12-14 20:28:38 +00:00
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virtual void sortRelocs(const MCAssembler &Asm,
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std::vector<ELFRelocationEntry> &Relocs);
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};
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class PPCELFRelocationEntry : public ELFRelocationEntry {
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public:
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PPCELFRelocationEntry(const ELFRelocationEntry &RE);
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bool operator<(const PPCELFRelocationEntry &RE) const {
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return (RE.r_offset < r_offset ||
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(RE.r_offset == r_offset && RE.Type > Type));
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}
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2011-12-22 01:57:09 +00:00
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};
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}
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2012-12-14 20:28:38 +00:00
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PPCELFRelocationEntry::PPCELFRelocationEntry(const ELFRelocationEntry &RE)
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: ELFRelocationEntry(RE.r_offset, RE.Index, RE.Type, RE.Symbol,
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RE.r_addend, *RE.Fixup) {}
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2011-12-22 01:57:09 +00:00
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PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
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: MCELFObjectTargetWriter(Is64Bit, OSABI,
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Is64Bit ? ELF::EM_PPC64 : ELF::EM_PPC,
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2011-12-22 18:38:06 +00:00
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/*HasRelocationAddend*/ true) {}
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2011-12-22 01:57:09 +00:00
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PPCELFObjectWriter::~PPCELFObjectWriter() {
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}
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2012-10-25 12:27:42 +00:00
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unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const
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{
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MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ?
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MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
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2011-12-22 01:57:09 +00:00
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// determine the type of the relocation
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unsigned Type;
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if (IsPCRel) {
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switch ((unsigned)Fixup.getKind()) {
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default:
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llvm_unreachable("Unimplemented");
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case PPC::fixup_ppc_br24:
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Type = ELF::R_PPC_REL24;
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break;
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2013-01-04 19:08:13 +00:00
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case FK_Data_4:
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2011-12-22 01:57:09 +00:00
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case FK_PCRel_4:
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Type = ELF::R_PPC_REL32;
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break;
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2013-01-04 19:08:13 +00:00
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case FK_Data_8:
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case FK_PCRel_8:
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Type = ELF::R_PPC64_REL64;
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break;
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2011-12-22 01:57:09 +00:00
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}
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} else {
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switch ((unsigned)Fixup.getKind()) {
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default: llvm_unreachable("invalid fixup kind!");
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case PPC::fixup_ppc_br24:
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Type = ELF::R_PPC_ADDR24;
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break;
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case PPC::fixup_ppc_brcond14:
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2012-10-25 12:27:42 +00:00
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Type = ELF::R_PPC_ADDR14; // XXX: or BRNTAKEN?_
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2011-12-22 01:57:09 +00:00
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break;
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case PPC::fixup_ppc_ha16:
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2012-11-13 19:24:36 +00:00
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switch (Modifier) {
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default: llvm_unreachable("Unsupported Modifier");
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case MCSymbolRefExpr::VK_PPC_TPREL16_HA:
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Type = ELF::R_PPC_TPREL16_HA;
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break;
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2012-12-12 19:29:35 +00:00
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case MCSymbolRefExpr::VK_PPC_DTPREL16_HA:
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Type = ELF::R_PPC64_DTPREL16_HA;
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break;
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2012-11-13 19:24:36 +00:00
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case MCSymbolRefExpr::VK_None:
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Type = ELF::R_PPC_ADDR16_HA;
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break;
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This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 17:35:46 +00:00
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case MCSymbolRefExpr::VK_PPC_TOC16_HA:
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Type = ELF::R_PPC64_TOC16_HA;
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break;
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This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14 17:02:38 +00:00
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case MCSymbolRefExpr::VK_PPC_GOT_TPREL16_HA:
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Type = ELF::R_PPC64_GOT_TPREL16_HA;
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break;
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This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 20:30:11 +00:00
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case MCSymbolRefExpr::VK_PPC_GOT_TLSGD16_HA:
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Type = ELF::R_PPC64_GOT_TLSGD16_HA;
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break;
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2012-12-12 19:29:35 +00:00
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case MCSymbolRefExpr::VK_PPC_GOT_TLSLD16_HA:
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Type = ELF::R_PPC64_GOT_TLSLD16_HA;
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break;
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2012-11-13 19:24:36 +00:00
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}
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2011-12-22 01:57:09 +00:00
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break;
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case PPC::fixup_ppc_lo16:
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2012-11-13 19:24:36 +00:00
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switch (Modifier) {
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default: llvm_unreachable("Unsupported Modifier");
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case MCSymbolRefExpr::VK_PPC_TPREL16_LO:
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Type = ELF::R_PPC_TPREL16_LO;
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break;
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2012-12-12 19:29:35 +00:00
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case MCSymbolRefExpr::VK_PPC_DTPREL16_LO:
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Type = ELF::R_PPC64_DTPREL16_LO;
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break;
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2012-11-13 19:24:36 +00:00
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case MCSymbolRefExpr::VK_None:
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Type = ELF::R_PPC_ADDR16_LO;
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break;
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This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 17:35:46 +00:00
|
|
|
case MCSymbolRefExpr::VK_PPC_TOC16_LO:
|
|
|
|
|
Type = ELF::R_PPC64_TOC16_LO;
|
|
|
|
|
break;
|
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 20:30:11 +00:00
|
|
|
case MCSymbolRefExpr::VK_PPC_GOT_TLSGD16_LO:
|
|
|
|
|
Type = ELF::R_PPC64_GOT_TLSGD16_LO;
|
|
|
|
|
break;
|
2012-12-12 19:29:35 +00:00
|
|
|
case MCSymbolRefExpr::VK_PPC_GOT_TLSLD16_LO:
|
|
|
|
|
Type = ELF::R_PPC64_GOT_TLSLD16_LO;
|
|
|
|
|
break;
|
2012-11-13 19:24:36 +00:00
|
|
|
}
|
2011-12-22 01:57:09 +00:00
|
|
|
break;
|
|
|
|
|
case PPC::fixup_ppc_lo14:
|
|
|
|
|
Type = ELF::R_PPC_ADDR14;
|
|
|
|
|
break;
|
2012-10-25 12:27:42 +00:00
|
|
|
case PPC::fixup_ppc_toc:
|
|
|
|
|
Type = ELF::R_PPC64_TOC;
|
|
|
|
|
break;
|
|
|
|
|
case PPC::fixup_ppc_toc16:
|
|
|
|
|
Type = ELF::R_PPC64_TOC16;
|
|
|
|
|
break;
|
|
|
|
|
case PPC::fixup_ppc_toc16_ds:
|
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 17:35:46 +00:00
|
|
|
switch (Modifier) {
|
|
|
|
|
default: llvm_unreachable("Unsupported Modifier");
|
|
|
|
|
case MCSymbolRefExpr::VK_PPC_TOC_ENTRY:
|
|
|
|
|
Type = ELF::R_PPC64_TOC16_DS;
|
|
|
|
|
break;
|
|
|
|
|
case MCSymbolRefExpr::VK_PPC_TOC16_LO:
|
|
|
|
|
Type = ELF::R_PPC64_TOC16_LO_DS;
|
|
|
|
|
break;
|
This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14 17:02:38 +00:00
|
|
|
case MCSymbolRefExpr::VK_PPC_GOT_TPREL16_LO:
|
|
|
|
|
Type = ELF::R_PPC64_GOT_TPREL16_LO_DS;
|
2012-12-04 16:18:08 +00:00
|
|
|
break;
|
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 17:35:46 +00:00
|
|
|
}
|
2012-10-25 12:27:42 +00:00
|
|
|
break;
|
2012-12-04 16:18:08 +00:00
|
|
|
case PPC::fixup_ppc_tlsreg:
|
|
|
|
|
Type = ELF::R_PPC64_TLS;
|
|
|
|
|
break;
|
2012-12-12 19:29:35 +00:00
|
|
|
case PPC::fixup_ppc_nofixup:
|
|
|
|
|
switch (Modifier) {
|
|
|
|
|
default: llvm_unreachable("Unsupported Modifier");
|
|
|
|
|
case MCSymbolRefExpr::VK_PPC_TLSGD:
|
|
|
|
|
Type = ELF::R_PPC64_TLSGD;
|
|
|
|
|
break;
|
|
|
|
|
case MCSymbolRefExpr::VK_PPC_TLSLD:
|
|
|
|
|
Type = ELF::R_PPC64_TLSLD;
|
|
|
|
|
break;
|
|
|
|
|
}
|
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 20:30:11 +00:00
|
|
|
break;
|
2012-10-25 12:27:42 +00:00
|
|
|
case FK_Data_8:
|
|
|
|
|
switch (Modifier) {
|
|
|
|
|
default: llvm_unreachable("Unsupported Modifier");
|
|
|
|
|
case MCSymbolRefExpr::VK_PPC_TOC:
|
|
|
|
|
Type = ELF::R_PPC64_TOC;
|
|
|
|
|
break;
|
|
|
|
|
case MCSymbolRefExpr::VK_None:
|
|
|
|
|
Type = ELF::R_PPC64_ADDR64;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
2011-12-22 01:57:09 +00:00
|
|
|
case FK_Data_4:
|
|
|
|
|
Type = ELF::R_PPC_ADDR32;
|
|
|
|
|
break;
|
|
|
|
|
case FK_Data_2:
|
|
|
|
|
Type = ELF::R_PPC_ADDR16;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return Type;
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-25 12:27:42 +00:00
|
|
|
unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target,
|
|
|
|
|
const MCFixup &Fixup,
|
|
|
|
|
bool IsPCRel,
|
|
|
|
|
bool IsRelocWithSymbol,
|
|
|
|
|
int64_t Addend) const {
|
|
|
|
|
return getRelocTypeInner(Target, Fixup, IsPCRel);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const MCSymbol *PPCELFObjectWriter::undefinedExplicitRelSym(const MCValue &Target,
|
|
|
|
|
const MCFixup &Fixup,
|
|
|
|
|
bool IsPCRel) const {
|
|
|
|
|
assert(Target.getSymA() && "SymA cannot be 0");
|
|
|
|
|
const MCSymbol &Symbol = Target.getSymA()->getSymbol().AliasedSymbol();
|
|
|
|
|
|
|
|
|
|
unsigned RelocType = getRelocTypeInner(Target, Fixup, IsPCRel);
|
|
|
|
|
|
|
|
|
|
// The .odp creation emits a relocation against the symbol ".TOC." which
|
|
|
|
|
// create a R_PPC64_TOC relocation. However the relocation symbol name
|
|
|
|
|
// in final object creation should be NULL, since the symbol does not
|
|
|
|
|
// really exist, it is just the reference to TOC base for the current
|
|
|
|
|
// object file.
|
|
|
|
|
bool EmitThisSym = RelocType != ELF::R_PPC64_TOC;
|
|
|
|
|
|
|
|
|
|
if (EmitThisSym && !Symbol.isTemporary())
|
|
|
|
|
return &Symbol;
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-22 01:57:09 +00:00
|
|
|
void PPCELFObjectWriter::
|
|
|
|
|
adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
|
|
|
|
|
switch ((unsigned)Fixup.getKind()) {
|
|
|
|
|
case PPC::fixup_ppc_ha16:
|
|
|
|
|
case PPC::fixup_ppc_lo16:
|
2012-10-25 14:29:13 +00:00
|
|
|
case PPC::fixup_ppc_toc16:
|
|
|
|
|
case PPC::fixup_ppc_toc16_ds:
|
2011-12-22 01:57:09 +00:00
|
|
|
RelocOffset += 2;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-14 20:28:38 +00:00
|
|
|
// The standard sorter only sorts on the r_offset field, but PowerPC can
|
|
|
|
|
// have multiple relocations at the same offset. Sort secondarily on the
|
|
|
|
|
// relocation type to avoid nondeterminism.
|
|
|
|
|
void PPCELFObjectWriter::sortRelocs(const MCAssembler &Asm,
|
|
|
|
|
std::vector<ELFRelocationEntry> &Relocs) {
|
|
|
|
|
|
|
|
|
|
// Copy to a temporary vector of relocation entries having a different
|
|
|
|
|
// sort function.
|
|
|
|
|
std::vector<PPCELFRelocationEntry> TmpRelocs;
|
|
|
|
|
|
|
|
|
|
for (std::vector<ELFRelocationEntry>::iterator R = Relocs.begin();
|
|
|
|
|
R != Relocs.end(); ++R) {
|
|
|
|
|
TmpRelocs.push_back(PPCELFRelocationEntry(*R));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Sort in place by ascending r_offset and descending r_type.
|
|
|
|
|
array_pod_sort(TmpRelocs.begin(), TmpRelocs.end());
|
|
|
|
|
|
|
|
|
|
// Copy back to the original vector.
|
|
|
|
|
unsigned I = 0;
|
|
|
|
|
for (std::vector<PPCELFRelocationEntry>::iterator R = TmpRelocs.begin();
|
|
|
|
|
R != TmpRelocs.end(); ++R, ++I) {
|
|
|
|
|
Relocs[I] = ELFRelocationEntry(R->r_offset, R->Index, R->Type,
|
|
|
|
|
R->Symbol, R->r_addend, *R->Fixup);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2011-12-22 01:57:09 +00:00
|
|
|
MCObjectWriter *llvm::createPPCELFObjectWriter(raw_ostream &OS,
|
|
|
|
|
bool Is64Bit,
|
|
|
|
|
uint8_t OSABI) {
|
|
|
|
|
MCELFObjectTargetWriter *MOTW = new PPCELFObjectWriter(Is64Bit, OSABI);
|
2011-12-22 18:38:06 +00:00
|
|
|
return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false);
|
2011-12-22 01:57:09 +00:00
|
|
|
}
|
