llvm-6502/test/CodeGen/PowerPC/ppc-prologue.ll

; RUN: llc < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s

define i32 @_Z4funci(i32 %a) ssp {
; CHECK:       mflr r0
; CHECK-NEXT:  stw r31, -4(r1)
; CHECK-NEXT:  stw r0, 8(r1)
; CHECK-NEXT:  stwu r1, -80(r1)
; CHECK:  mr r31, r1
entry:
  %a_addr = alloca i32                            ; <i32*> [#uses=2]
  %retval = alloca i32                            ; <i32*> [#uses=2]
  %0 = alloca i32                                 ; <i32*> [#uses=2]
  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
  store i32 %a, i32* %a_addr
  %1 = call i32 @_Z3barPi(i32* %a_addr)           ; <i32> [#uses=1]
  store i32 %1, i32* %0, align 4
  %2 = load i32, i32* %0, align 4                      ; <i32> [#uses=1]
  store i32 %2, i32* %retval, align 4
  br label %return

return:                                           ; preds = %entry
  %retval1 = load i32, i32* %retval                    ; <i32> [#uses=1]
  ret i32 %retval1
}

declare i32 @_Z3barPi(i32*)
Fix test to work on every platform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86786 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-11 01:44:22 +00:00			`; RUN: llc < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim \| FileCheck %s`
Modify how the prologue encoded the "move" information for the FDE. GCC generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-10 22:14:04 +00:00
			`define i32 @_Z4funci(i32 %a) ssp {`
			`; CHECK: mflr r0`
Do not store R31 into the caller's link area on PPC. This violates the ABI (that area is "reserved"), and while it is safe if all code is generated with current compilers, there is some very old code around that uses that slot for something else, and breaks if it is stored into. Adjust testcases looking for current behavior. I've verified that the stack frame size is right in all testcases, whether it changed or not. 7311323. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89811 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-24 22:59:02 +00:00			`; CHECK-NEXT: stw r31, -4(r1)`
Modify how the prologue encoded the "move" information for the FDE. GCC generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-10 22:14:04 +00:00			`; CHECK-NEXT: stw r0, 8(r1)`
			`; CHECK-NEXT: stwu r1, -80(r1)`
Add 130690 back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130693 91177308-0d34-0410-b5e6-96231b3b80d8 2011-05-02 15:58:16 +00:00			`; CHECK: mr r31, r1`
Modify how the prologue encoded the "move" information for the FDE. GCC generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-10 22:14:04 +00:00			`entry:`
			`%a_addr = alloca i32 ; <i32*> [#uses=2]`
			`%retval = alloca i32 ; <i32*> [#uses=2]`
			`%0 = alloca i32 ; <i32*> [#uses=2]`
			`%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]`
			`store i32 %a, i32* %a_addr`
			`%1 = call i32 @_Z3barPi(i32* %a_addr) ; <i32> [#uses=1]`
			`store i32 %1, i32* %0, align 4`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8 2015-02-27 21:17:42 +00:00			`%2 = load i32, i32* %0, align 4 ; <i32> [#uses=1]`
Modify how the prologue encoded the "move" information for the FDE. GCC generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-10 22:14:04 +00:00			`store i32 %2, i32* %retval, align 4`
			`br label %return`

			`return: ; preds = %entry`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8 2015-02-27 21:17:42 +00:00			`%retval1 = load i32, i32* %retval ; <i32> [#uses=1]`
Modify how the prologue encoded the "move" information for the FDE. GCC generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86729 91177308-0d34-0410-b5e6-96231b3b80d8 2009-11-10 22:14:04 +00:00			`ret i32 %retval1`
			`}`

			`declare i32 @_Z3barPi(i32*)`