llvm-6502/test/CodeGen/X86/vec_set-D.ll

; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s

; CHECK: movq

define <4 x i32> @t(i32 %x, i32 %y) nounwind  {
	%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
	%tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
	ret <4 x i32> %tmp2
}
More rewrites of x86 codegen regression tests with FileCheck git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180837 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-01 05:34:30 +00:00			`; RUN: llc < %s -march=x86 -mattr=+sse2 \| FileCheck %s`

			`; CHECK: movq`
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8 2008-05-08 00:57:18 +00:00
			`define <4 x i32> @t(i32 %x, i32 %y) nounwind {`
			`%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0`
			`%tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1`
			`ret <4 x i32> %tmp2`
			`}`