mirror of
https://github.com/c64scene-ar/llvm-6502.git
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75 lines
2.2 KiB
LLVM
75 lines
2.2 KiB
LLVM
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; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
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define signext i8 @test_vminv_s8(<8 x i8> %a1) {
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; CHECK: test_vminv_s8
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; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v8i8(<8 x i8> %a1)
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%0 = trunc i32 %vminv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vminv_s16(<4 x i16> %a1) {
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; CHECK: test_vminv_s16
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; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v4i16(<4 x i16> %a1)
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%0 = trunc i32 %vminv.i to i16
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ret i16 %0
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}
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define i32 @test_vminv_s32(<2 x i32> %a1) {
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; CHECK: test_vminv_s32
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; 2 x i32 is not supported by the ISA, thus, this is a special case
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; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v2i32(<2 x i32> %a1)
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ret i32 %vminv.i
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}
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define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
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; CHECK: test_vminvq_s8
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; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v16i8(<16 x i8> %a1)
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%0 = trunc i32 %vminv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
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; CHECK: test_vminvq_s16
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; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v8i16(<8 x i16> %a1)
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%0 = trunc i32 %vminv.i to i16
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ret i16 %0
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}
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define i32 @test_vminvq_s32(<4 x i32> %a1) {
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; CHECK: test_vminvq_s32
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; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
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; CHECK-NEXT: fmov w0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v4i32(<4 x i32> %a1)
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ret i32 %vminv.i
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}
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declare i32 @llvm.arm64.neon.sminv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.arm64.neon.sminv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.arm64.neon.sminv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.arm64.neon.sminv.i32.v2i32(<2 x i32>)
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declare i32 @llvm.arm64.neon.sminv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.arm64.neon.sminv.i32.v8i8(<8 x i8>)
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