mirror of
https://github.com/c64scene-ar/llvm-6502.git
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581 lines
26 KiB
C++
581 lines
26 KiB
C++
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//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AArch64FixupKinds.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class AArch64AsmBackend : public MCAsmBackend {
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const MCSubtargetInfo* STI;
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public:
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AArch64AsmBackend(const Target &T, const StringRef TT)
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: MCAsmBackend(),
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STI(AArch64_MC::createAArch64MCSubtargetInfo(TT, "", ""))
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{}
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~AArch64AsmBackend() {
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delete STI;
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}
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
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virtual void processFixupValue(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFixup &Fixup, const MCFragment *DF,
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MCValue &Target, uint64_t &Value,
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bool &IsResolved);
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};
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} // end anonymous namespace
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void AArch64AsmBackend::processFixupValue(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFixup &Fixup,
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const MCFragment *DF,
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MCValue &Target, uint64_t &Value,
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bool &IsResolved) {
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// The ADRP instruction adds some multiple of 0x1000 to the current PC &
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// ~0xfff. This means that the required offset to reach a symbol can vary by
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// up to one step depending on where the ADRP is in memory. For example:
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//
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// ADRP x0, there
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// there:
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//
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// If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
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// we'll need that as an offset. At any other address "there" will be in the
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// same page as the ADRP and the instruction should encode 0x0. Assuming the
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// section isn't 0x1000-aligned, we therefore need to delegate this decision
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// to the linker -- a relocation!
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if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_page ||
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(uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_got_page ||
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(uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_gottprel_page ||
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(uint32_t)Fixup.getKind() == AArch64::fixup_a64_tlsdesc_adr_page)
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IsResolved = false;
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}
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static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value);
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namespace {
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class ELFAArch64AsmBackend : public AArch64AsmBackend {
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public:
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uint8_t OSABI;
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ELFAArch64AsmBackend(const Target &T, const StringRef TT,
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uint8_t _OSABI)
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: AArch64AsmBackend(T, TT), OSABI(_OSABI) { }
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const;
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unsigned int getNumFixupKinds() const {
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return AArch64::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// AArch64FixupKinds.h.
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//
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// Name Offset (bits) Size (bits) Flags
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{ "fixup_a64_ld_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_adr_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_adr_prel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_add_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst8_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst16_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst32_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst64_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst128_lo12", 0, 32, 0 },
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{ "fixup_a64_tstbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_condbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_uncondbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_call", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_movw_uabs_g0", 0, 32, 0 },
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{ "fixup_a64_movw_uabs_g0_nc", 0, 32, 0 },
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{ "fixup_a64_movw_uabs_g1", 0, 32, 0 },
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{ "fixup_a64_movw_uabs_g1_nc", 0, 32, 0 },
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{ "fixup_a64_movw_uabs_g2", 0, 32, 0 },
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{ "fixup_a64_movw_uabs_g2_nc", 0, 32, 0 },
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{ "fixup_a64_movw_uabs_g3", 0, 32, 0 },
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{ "fixup_a64_movw_sabs_g0", 0, 32, 0 },
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{ "fixup_a64_movw_sabs_g1", 0, 32, 0 },
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{ "fixup_a64_movw_sabs_g2", 0, 32, 0 },
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{ "fixup_a64_adr_prel_got_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_ld64_got_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_movw_dtprel_g2", 0, 32, 0 },
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{ "fixup_a64_movw_dtprel_g1", 0, 32, 0 },
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{ "fixup_a64_movw_dtprel_g1_nc", 0, 32, 0 },
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{ "fixup_a64_movw_dtprel_g0", 0, 32, 0 },
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{ "fixup_a64_movw_dtprel_g0_nc", 0, 32, 0 },
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{ "fixup_a64_add_dtprel_hi12", 0, 32, 0 },
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{ "fixup_a64_add_dtprel_lo12", 0, 32, 0 },
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{ "fixup_a64_add_dtprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst8_dtprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst8_dtprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst16_dtprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst16_dtprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst32_dtprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst32_dtprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst64_dtprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst64_dtprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_movw_gottprel_g1", 0, 32, 0 },
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{ "fixup_a64_movw_gottprel_g0_nc", 0, 32, 0 },
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{ "fixup_a64_adr_gottprel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_ld64_gottprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ld_gottprel_prel19", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_movw_tprel_g2", 0, 32, 0 },
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{ "fixup_a64_movw_tprel_g1", 0, 32, 0 },
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{ "fixup_a64_movw_tprel_g1_nc", 0, 32, 0 },
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{ "fixup_a64_movw_tprel_g0", 0, 32, 0 },
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{ "fixup_a64_movw_tprel_g0_nc", 0, 32, 0 },
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{ "fixup_a64_add_tprel_hi12", 0, 32, 0 },
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{ "fixup_a64_add_tprel_lo12", 0, 32, 0 },
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{ "fixup_a64_add_tprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst8_tprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst8_tprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst16_tprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst16_tprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst32_tprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst32_tprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_ldst64_tprel_lo12", 0, 32, 0 },
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{ "fixup_a64_ldst64_tprel_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_tlsdesc_adr_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_a64_tlsdesc_ld64_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_tlsdesc_add_lo12_nc", 0, 32, 0 },
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{ "fixup_a64_tlsdesc_call", 0, 0, 0 }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const {
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unsigned NumBytes = getFixupKindInfo(Fixup.getKind()).TargetSize / 8;
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Value = adjustFixupValue(Fixup.getKind(), Value);
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if (!Value) return; // Doesn't change encoding.
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unsigned Offset = Fixup.getOffset();
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assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the bits
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// from the fixup value.
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for (unsigned i = 0; i != NumBytes; ++i) {
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Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
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}
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}
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bool mayNeedRelaxation(const MCInst&) const {
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return false;
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}
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void relaxInstruction(const MCInst&, llvm::MCInst&) const {
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llvm_unreachable("Cannot relax instructions");
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}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createAArch64ELFObjectWriter(OS, OSABI);
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}
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};
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} // end anonymous namespace
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bool
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ELFAArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const {
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// Correct for now. With all instructions 32-bit only very low-level
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// considerations could make you select something which may fail.
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return false;
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}
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bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// Can't emit NOP with size not multiple of 32-bits
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if (Count % 4 != 0)
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return false;
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write32(0xd503201f);
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return true;
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}
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static unsigned ADRImmBits(unsigned Value) {
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unsigned lo2 = Value & 0x3;
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unsigned hi19 = (Value & 0x1fffff) >> 2;
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return (hi19 << 5) | (lo2 << 29);
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}
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static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_2:
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assert((int64_t)Value >= -32768 &&
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(int64_t)Value <= 65536 &&
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"Out of range ABS16 fixup");
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return Value;
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case FK_Data_4:
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assert((int64_t)Value >= -(1LL << 31) &&
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(int64_t)Value <= (1LL << 32) - 1 &&
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"Out of range ABS32 fixup");
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return Value;
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case FK_Data_8:
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return Value;
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case AArch64::fixup_a64_ld_gottprel_prel19:
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// R_AARCH64_LD_GOTTPREL_PREL19: Set a load-literal immediate to bits 1F
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// FFFC of G(TPREL(S+A)) - P; check -2^20 <= X < 2^20.
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case AArch64::fixup_a64_ld_prel:
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// R_AARCH64_LD_PREL_LO19: Sets a load-literal (immediate) value to bits
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// 1F FFFC of S+A-P, checking that -2^20 <= S+A-P < 2^20.
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assert((int64_t)Value >= -(1LL << 20) &&
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(int64_t)Value < (1LL << 20) && "Out of range LDR (lit) fixup");
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return (Value & 0x1ffffc) << 3;
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case AArch64::fixup_a64_adr_prel:
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// R_AARCH64_ADR_PREL_LO21: Sets an ADR immediate value to bits 1F FFFF of
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// the result of S+A-P, checking that -2^20 <= S+A-P < 2^20.
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assert((int64_t)Value >= -(1LL << 20) &&
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(int64_t)Value < (1LL << 20) && "Out of range ADR fixup");
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return ADRImmBits(Value & 0x1fffff);
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case AArch64::fixup_a64_adr_prel_page:
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// R_AARCH64_ADR_PREL_PG_HI21: Sets an ADRP immediate value to bits 1 FFFF
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// F000 of the result of the operation, checking that -2^32 <= result <
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// 2^32.
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assert((int64_t)Value >= -(1LL << 32) &&
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(int64_t)Value < (1LL << 32) && "Out of range ADRP fixup");
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return ADRImmBits((Value & 0x1fffff000ULL) >> 12);
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case AArch64::fixup_a64_add_dtprel_hi12:
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// R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits
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// FF F000 of DTPREL(S+A), check 0 <= X < 2^24.
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case AArch64::fixup_a64_add_tprel_hi12:
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// R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits
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// FF F000 of TPREL(S+A), check 0 <= X < 2^24.
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assert((int64_t)Value >= 0 &&
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(int64_t)Value < (1LL << 24) && "Out of range ADD fixup");
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return (Value & 0xfff000) >> 2;
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case AArch64::fixup_a64_add_dtprel_lo12:
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// R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits
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// FFF of DTPREL(S+A), check 0 <= X < 2^12.
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case AArch64::fixup_a64_add_tprel_lo12:
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// R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits
|
||
|
|
// FFF of TPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
assert((int64_t)Value >= 0 &&
|
||
|
|
(int64_t)Value < (1LL << 12) && "Out of range ADD fixup");
|
||
|
|
// ... fallthrough to no-checking versions ...
|
||
|
|
case AArch64::fixup_a64_add_dtprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: Set an ADD immediate field to bits
|
||
|
|
// FFF of DTPREL(S+A) with no overflow check.
|
||
|
|
case AArch64::fixup_a64_add_tprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_ADD_TPREL_LO12_NC: Set an ADD immediate field to bits
|
||
|
|
// FFF of TPREL(S+A) with no overflow check.
|
||
|
|
case AArch64::fixup_a64_tlsdesc_add_lo12_nc:
|
||
|
|
// R_AARCH64_TLSDESC_ADD_LO12_NC: Set an ADD immediate field to bits
|
||
|
|
// FFF of G(TLSDESC(S+A)), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_add_lo12:
|
||
|
|
// R_AARCH64_ADD_ABS_LO12_NC: Sets an ADD immediate value to bits FFF of
|
||
|
|
// S+A, with no overflow check.
|
||
|
|
return (Value & 0xfff) << 10;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_ldst8_dtprel_lo12:
|
||
|
|
// R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
case AArch64::fixup_a64_ldst8_tprel_lo12:
|
||
|
|
// R_AARCH64_TLSLE_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
assert((int64_t) Value >= 0 &&
|
||
|
|
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
|
||
|
|
// ... fallthrough to no-checking versions ...
|
||
|
|
case AArch64::fixup_a64_ldst8_dtprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF
|
||
|
|
// of DTPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst8_tprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF
|
||
|
|
// of TPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst8_lo12:
|
||
|
|
// R_AARCH64_LDST8_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFF
|
||
|
|
// of S+A, with no overflow check.
|
||
|
|
return (Value & 0xfff) << 10;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_ldst16_dtprel_lo12:
|
||
|
|
// R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
case AArch64::fixup_a64_ldst16_tprel_lo12:
|
||
|
|
// R_AARCH64_TLSLE_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
assert((int64_t) Value >= 0 &&
|
||
|
|
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
|
||
|
|
// ... fallthrough to no-checking versions ...
|
||
|
|
case AArch64::fixup_a64_ldst16_dtprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE
|
||
|
|
// of DTPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst16_tprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE
|
||
|
|
// of TPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst16_lo12:
|
||
|
|
// R_AARCH64_LDST16_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFE
|
||
|
|
// of S+A, with no overflow check.
|
||
|
|
return (Value & 0xffe) << 9;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_ldst32_dtprel_lo12:
|
||
|
|
// R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
case AArch64::fixup_a64_ldst32_tprel_lo12:
|
||
|
|
// R_AARCH64_TLSLE_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
assert((int64_t) Value >= 0 &&
|
||
|
|
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
|
||
|
|
// ... fallthrough to no-checking versions ...
|
||
|
|
case AArch64::fixup_a64_ldst32_dtprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC
|
||
|
|
// of DTPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst32_tprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC
|
||
|
|
// of TPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst32_lo12:
|
||
|
|
// R_AARCH64_LDST32_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFC
|
||
|
|
// of S+A, with no overflow check.
|
||
|
|
return (Value & 0xffc) << 8;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_ldst64_dtprel_lo12:
|
||
|
|
// R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
case AArch64::fixup_a64_ldst64_tprel_lo12:
|
||
|
|
// R_AARCH64_TLSLE_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8
|
||
|
|
// of DTPREL(S+A), check 0 <= X < 2^12.
|
||
|
|
assert((int64_t) Value >= 0 &&
|
||
|
|
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
|
||
|
|
// ... fallthrough to no-checking versions ...
|
||
|
|
case AArch64::fixup_a64_ldst64_dtprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8
|
||
|
|
// of DTPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst64_tprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSLD_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8
|
||
|
|
// of TPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_ldst64_lo12:
|
||
|
|
// R_AARCH64_LDST64_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF8
|
||
|
|
// of S+A, with no overflow check.
|
||
|
|
return (Value & 0xff8) << 7;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_ldst128_lo12:
|
||
|
|
// R_AARCH64_LDST128_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF0
|
||
|
|
// of S+A, with no overflow check.
|
||
|
|
return (Value & 0xff0) << 6;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_uabs_g0:
|
||
|
|
// R_AARCH64_MOVW_UABS_G0: Sets a MOVZ immediate field to bits FFFF of S+A
|
||
|
|
// with a check that S+A < 2^16
|
||
|
|
assert(Value <= 0xffff && "Out of range move wide fixup");
|
||
|
|
return (Value & 0xffff) << 5;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_dtprel_g0_nc:
|
||
|
|
// R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: Sets a MOVK immediate field to bits
|
||
|
|
// FFFF of DTPREL(S+A) with no overflow check.
|
||
|
|
case AArch64::fixup_a64_movw_gottprel_g0_nc:
|
||
|
|
// R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: Sets a MOVK immediate field to bits
|
||
|
|
// FFFF of G(TPREL(S+A)) - GOT with no overflow check.
|
||
|
|
case AArch64::fixup_a64_movw_tprel_g0_nc:
|
||
|
|
// R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: Sets a MOVK immediate field to bits
|
||
|
|
// FFFF of TPREL(S+A) with no overflow check.
|
||
|
|
case AArch64::fixup_a64_movw_uabs_g0_nc:
|
||
|
|
// R_AARCH64_MOVW_UABS_G0_NC: Sets a MOVK immediate field to bits FFFF of
|
||
|
|
// S+A with no overflow check.
|
||
|
|
return (Value & 0xffff) << 5;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_uabs_g1:
|
||
|
|
// R_AARCH64_MOVW_UABS_G1: Sets a MOVZ immediate field to bits FFFF0000 of
|
||
|
|
// S+A with a check that S+A < 2^32
|
||
|
|
assert(Value <= 0xffffffffull && "Out of range move wide fixup");
|
||
|
|
return ((Value >> 16) & 0xffff) << 5;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_dtprel_g1_nc:
|
||
|
|
// R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: Set a MOVK immediate field
|
||
|
|
// to bits FFFF0000 of DTPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_movw_tprel_g1_nc:
|
||
|
|
// R_AARCH64_TLSLD_MOVW_TPREL_G1_NC: Set a MOVK immediate field
|
||
|
|
// to bits FFFF0000 of TPREL(S+A), with no overflow check.
|
||
|
|
case AArch64::fixup_a64_movw_uabs_g1_nc:
|
||
|
|
// R_AARCH64_MOVW_UABS_G1_NC: Sets a MOVK immediate field to bits
|
||
|
|
// FFFF0000 of S+A with no overflow check.
|
||
|
|
return ((Value >> 16) & 0xffff) << 5;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_uabs_g2:
|
||
|
|
// R_AARCH64_MOVW_UABS_G2: Sets a MOVZ immediate field to bits FFFF 0000
|
||
|
|
// 0000 of S+A with a check that S+A < 2^48
|
||
|
|
assert(Value <= 0xffffffffffffull && "Out of range move wide fixup");
|
||
|
|
return ((Value >> 32) & 0xffff) << 5;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_uabs_g2_nc:
|
||
|
|
// R_AARCH64_MOVW_UABS_G2: Sets a MOVK immediate field to bits FFFF 0000
|
||
|
|
// 0000 of S+A with no overflow check.
|
||
|
|
return ((Value >> 32) & 0xffff) << 5;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_uabs_g3:
|
||
|
|
// R_AARCH64_MOVW_UABS_G3: Sets a MOVZ immediate field to bits FFFF 0000
|
||
|
|
// 0000 0000 of S+A (no overflow check needed)
|
||
|
|
return ((Value >> 48) & 0xffff) << 5;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_dtprel_g0:
|
||
|
|
// R_AARCH64_TLSLD_MOVW_DTPREL_G0: Set a MOV[NZ] immediate field
|
||
|
|
// to bits FFFF of DTPREL(S+A).
|
||
|
|
case AArch64::fixup_a64_movw_tprel_g0:
|
||
|
|
// R_AARCH64_TLSLE_MOVW_TPREL_G0: Set a MOV[NZ] immediate field to
|
||
|
|
// bits FFFF of TPREL(S+A).
|
||
|
|
case AArch64::fixup_a64_movw_sabs_g0: {
|
||
|
|
// R_AARCH64_MOVW_SABS_G0: Sets MOV[NZ] immediate field using bits FFFF of
|
||
|
|
// S+A (see notes below); check -2^16 <= S+A < 2^16. (notes say that we
|
||
|
|
// should convert between MOVN and MOVZ to achieve our goals).
|
||
|
|
int64_t Signed = Value;
|
||
|
|
assert(Signed >= -(1LL << 16) && Signed < (1LL << 16)
|
||
|
|
&& "Out of range move wide fixup");
|
||
|
|
if (Signed >= 0) {
|
||
|
|
Value = (Value & 0xffff) << 5;
|
||
|
|
// Bit 30 converts the MOVN encoding into a MOVZ
|
||
|
|
Value |= 1 << 30;
|
||
|
|
} else {
|
||
|
|
// MCCodeEmitter should have encoded a MOVN, which is fine.
|
||
|
|
Value = (~Value & 0xffff) << 5;
|
||
|
|
}
|
||
|
|
return Value;
|
||
|
|
}
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_dtprel_g1:
|
||
|
|
// R_AARCH64_TLSLD_MOVW_DTPREL_G1: Set a MOV[NZ] immediate field
|
||
|
|
// to bits FFFF0000 of DTPREL(S+A).
|
||
|
|
case AArch64::fixup_a64_movw_gottprel_g1:
|
||
|
|
// R_AARCH64_TLSIE_MOVW_GOTTPREL_G1: Set a MOV[NZ] immediate field
|
||
|
|
// to bits FFFF0000 of G(TPREL(S+A)) - GOT.
|
||
|
|
case AArch64::fixup_a64_movw_tprel_g1:
|
||
|
|
// R_AARCH64_TLSLE_MOVW_TPREL_G1: Set a MOV[NZ] immediate field to
|
||
|
|
// bits FFFF0000 of TPREL(S+A).
|
||
|
|
case AArch64::fixup_a64_movw_sabs_g1: {
|
||
|
|
// R_AARCH64_MOVW_SABS_G1: Sets MOV[NZ] immediate field using bits FFFF 0000
|
||
|
|
// of S+A (see notes below); check -2^32 <= S+A < 2^32. (notes say that we
|
||
|
|
// should convert between MOVN and MOVZ to achieve our goals).
|
||
|
|
int64_t Signed = Value;
|
||
|
|
assert(Signed >= -(1LL << 32) && Signed < (1LL << 32)
|
||
|
|
&& "Out of range move wide fixup");
|
||
|
|
if (Signed >= 0) {
|
||
|
|
Value = ((Value >> 16) & 0xffff) << 5;
|
||
|
|
// Bit 30 converts the MOVN encoding into a MOVZ
|
||
|
|
Value |= 1 << 30;
|
||
|
|
} else {
|
||
|
|
Value = ((~Value >> 16) & 0xffff) << 5;
|
||
|
|
}
|
||
|
|
return Value;
|
||
|
|
}
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_movw_dtprel_g2:
|
||
|
|
// R_AARCH64_TLSLD_MOVW_DTPREL_G2: Set a MOV[NZ] immediate field
|
||
|
|
// to bits FFFF 0000 0000 of DTPREL(S+A).
|
||
|
|
case AArch64::fixup_a64_movw_tprel_g2:
|
||
|
|
// R_AARCH64_TLSLE_MOVW_TPREL_G2: Set a MOV[NZ] immediate field to
|
||
|
|
// bits FFFF 0000 0000 of TPREL(S+A).
|
||
|
|
case AArch64::fixup_a64_movw_sabs_g2: {
|
||
|
|
// R_AARCH64_MOVW_SABS_G2: Sets MOV[NZ] immediate field using bits FFFF 0000
|
||
|
|
// 0000 of S+A (see notes below); check -2^48 <= S+A < 2^48. (notes say that
|
||
|
|
// we should convert between MOVN and MOVZ to achieve our goals).
|
||
|
|
int64_t Signed = Value;
|
||
|
|
assert(Signed >= -(1LL << 48) && Signed < (1LL << 48)
|
||
|
|
&& "Out of range move wide fixup");
|
||
|
|
if (Signed >= 0) {
|
||
|
|
Value = ((Value >> 32) & 0xffff) << 5;
|
||
|
|
// Bit 30 converts the MOVN encoding into a MOVZ
|
||
|
|
Value |= 1 << 30;
|
||
|
|
} else {
|
||
|
|
Value = ((~Value >> 32) & 0xffff) << 5;
|
||
|
|
}
|
||
|
|
return Value;
|
||
|
|
}
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_tstbr:
|
||
|
|
// R_AARCH64_TSTBR14: Sets the immediate field of a TBZ/TBNZ instruction to
|
||
|
|
// bits FFFC of S+A-P, checking -2^15 <= S+A-P < 2^15.
|
||
|
|
assert((int64_t)Value >= -(1LL << 15) &&
|
||
|
|
(int64_t)Value < (1LL << 15) && "Out of range TBZ/TBNZ fixup");
|
||
|
|
return (Value & 0xfffc) << (5 - 2);
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_condbr:
|
||
|
|
// R_AARCH64_CONDBR19: Sets the immediate field of a conditional branch
|
||
|
|
// instruction to bits 1FFFFC of S+A-P, checking -2^20 <= S+A-P < 2^20.
|
||
|
|
assert((int64_t)Value >= -(1LL << 20) &&
|
||
|
|
(int64_t)Value < (1LL << 20) && "Out of range B.cond fixup");
|
||
|
|
return (Value & 0x1ffffc) << (5 - 2);
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_uncondbr:
|
||
|
|
// R_AARCH64_JUMP26 same as below (except to a linker, possibly).
|
||
|
|
case AArch64::fixup_a64_call:
|
||
|
|
// R_AARCH64_CALL26: Sets a CALL immediate field to bits FFFFFFC of S+A-P,
|
||
|
|
// checking that -2^27 <= S+A-P < 2^27.
|
||
|
|
assert((int64_t)Value >= -(1LL << 27) &&
|
||
|
|
(int64_t)Value < (1LL << 27) && "Out of range branch fixup");
|
||
|
|
return (Value & 0xffffffc) >> 2;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_adr_gottprel_page:
|
||
|
|
// R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: Set an ADRP immediate field to bits
|
||
|
|
// 1FFFFF000 of Page(G(TPREL(S+A))) - Page(P); check -2^32 <= X < 2^32.
|
||
|
|
case AArch64::fixup_a64_tlsdesc_adr_page:
|
||
|
|
// R_AARCH64_TLSDESC_ADR_PAGE: Set an ADRP immediate field to bits 1FFFFF000
|
||
|
|
// of Page(G(TLSDESC(S+A))) - Page(P); check -2^32 <= X < 2^32.
|
||
|
|
case AArch64::fixup_a64_adr_prel_got_page:
|
||
|
|
// R_AARCH64_ADR_GOT_PAGE: Sets the immediate value of an ADRP to bits
|
||
|
|
// 1FFFFF000 of the operation, checking that -2^32 < Page(G(S))-Page(GOT) <
|
||
|
|
// 2^32.
|
||
|
|
assert((int64_t)Value >= -(1LL << 32) &&
|
||
|
|
(int64_t)Value < (1LL << 32) && "Out of range ADRP fixup");
|
||
|
|
return ADRImmBits((Value & 0x1fffff000) >> 12);
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_ld64_gottprel_lo12_nc:
|
||
|
|
// R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: Set an LD offset field to bits FF8
|
||
|
|
// of X, with no overflow check. Check that X & 7 == 0.
|
||
|
|
case AArch64::fixup_a64_tlsdesc_ld64_lo12_nc:
|
||
|
|
// R_AARCH64_TLSDESC_LD64_LO12_NC: Set an LD offset field to bits FF8 of
|
||
|
|
// G(TLSDESC(S+A)), with no overflow check. Check that X & 7 == 0.
|
||
|
|
case AArch64::fixup_a64_ld64_got_lo12_nc:
|
||
|
|
// R_AARCH64_LD64_GOT_LO12_NC: Sets the LD/ST immediate field to bits FF8 of
|
||
|
|
// G(S) with no overflow check. Check X & 7 == 0
|
||
|
|
assert(((int64_t)Value & 7) == 0 && "Misaligned fixup");
|
||
|
|
return (Value & 0xff8) << 7;
|
||
|
|
|
||
|
|
case AArch64::fixup_a64_tlsdesc_call:
|
||
|
|
// R_AARCH64_TLSDESC_CALL: For relaxation only.
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
MCAsmBackend *
|
||
|
|
llvm::createAArch64AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
|
||
|
|
Triple TheTriple(TT);
|
||
|
|
|
||
|
|
return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS());
|
||
|
|
}
|