llvm-6502/test/CodeGen/R600/floor.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s

;CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

define void @test() {
   %r0 = call float @llvm.R600.load.input(i32 0)
   %r1 = call float @floor(float %r0)
   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
   ret void
}

declare float @llvm.R600.load.input(i32) readnone

declare void @llvm.AMDGPU.store.output(float, i32)

declare float @floor(float) readonly
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00			`;RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s`

R600: Schedule copy from phys register at beginning of block It allows regalloc pass to remove them by trivially assigning associated reg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8 2013-06-05 20:27:35 +00:00			`;CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}`
Add R600 backend A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-11 21:25:42 +00:00
			`define void @test() {`
			`%r0 = call float @llvm.R600.load.input(i32 0)`
			`%r1 = call float @floor(float %r0)`
			`call void @llvm.AMDGPU.store.output(float %r1, i32 0)`
			`ret void`
			`}`

			`declare float @llvm.R600.load.input(i32) readnone`

			`declare void @llvm.AMDGPU.store.output(float, i32)`

			`declare float @floor(float) readonly`