llvm-6502/test/CodeGen/R600/lshl.ll

;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s

;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 1

define void @test(i32 %p) {
   %i = mul i32 %p, 2
   %r = bitcast i32 %i to float
   call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)
   ret void
}

declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
R600/SI: Add processor types for each SI variant Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178928 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-05 23:31:35 +00:00			`;RUN: llc < %s -march=r600 -mcpu=verde \| FileCheck %s`
R600/SI: add srl/sha patterns for SI Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178125 91177308-0d34-0410-b5e6-96231b3b80d8 2013-03-27 09:12:44 +00:00
R600/SI: Add more special cases for opcodes to ensureSRegLimit() Also factor out the register class lookup to its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8 2013-08-06 23:08:18 +00:00			`;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 1`
R600/SI: add srl/sha patterns for SI Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178125 91177308-0d34-0410-b5e6-96231b3b80d8 2013-03-27 09:12:44 +00:00
			`define void @test(i32 %p) {`
			`%i = mul i32 %p, 2`
			`%r = bitcast i32 %i to float`
			`call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)`
			`ret void`
			`}`

			`declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone`

			`declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)`