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llvm-6502/test/CodeGen/Mips/msa/i10.ll

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[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 12:14:50 +00:00
; Test the MSA intrinsics that are encoded with the I10 instruction format.
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 10:08:31 +00:00
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 11:04:16 +00:00
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 12:14:50 +00:00
@llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
define i32 @llvm_mips_bnz_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bnz_b_ARG1
%1 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %0)
%2 = icmp eq i32 %1, 0
br i1 %2, label %true, label %false
true:
ret i32 2
false:
ret i32 3
}
declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind
; CHECK: llvm_mips_bnz_b_test:
; CHECK-DAG: ld.b [[R0:\$w[0-9]+]]
; CHECK-DAG: bnz.b [[R0]]
; CHECK: .size llvm_mips_bnz_b_test
@llvm_mips_bnz_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
define i32 @llvm_mips_bnz_h_test() nounwind {
entry:
%0 = load <8 x i16>* @llvm_mips_bnz_h_ARG1
%1 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %0)
%2 = icmp eq i32 %1, 0
br i1 %2, label %true, label %false
true:
ret i32 2
false:
ret i32 3
}
declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind
; CHECK: llvm_mips_bnz_h_test:
; CHECK-DAG: ld.h [[R0:\$w[0-9]+]]
; CHECK-DAG: bnz.h [[R0]]
; CHECK: .size llvm_mips_bnz_h_test
@llvm_mips_bnz_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
define i32 @llvm_mips_bnz_w_test() nounwind {
entry:
%0 = load <4 x i32>* @llvm_mips_bnz_w_ARG1
%1 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %0)
%2 = icmp eq i32 %1, 0
br i1 %2, label %true, label %false
true:
ret i32 2
false:
ret i32 3
}
declare i32 @llvm.mips.bnz.w(<4 x i32>) nounwind
; CHECK: llvm_mips_bnz_w_test:
; CHECK-DAG: ld.w [[R0:\$w[0-9]+]]
; CHECK-DAG: bnz.w [[R0]]
; CHECK: .size llvm_mips_bnz_w_test
@llvm_mips_bnz_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
define i32 @llvm_mips_bnz_d_test() nounwind {
entry:
%0 = load <2 x i64>* @llvm_mips_bnz_d_ARG1
%1 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %0)
%2 = icmp eq i32 %1, 0
br i1 %2, label %true, label %false
true:
ret i32 2
false:
ret i32 3
}
declare i32 @llvm.mips.bnz.d(<2 x i64>) nounwind
; CHECK: llvm_mips_bnz_d_test:
; CHECK-DAG: ld.d [[R0:\$w[0-9]+]]
; CHECK-DAG: bnz.d [[R0]]
; CHECK: .size llvm_mips_bnz_d_test
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