llvm-6502/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s

# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;

# CHECK: warning: potentially undefined instruction encoding
0x5f 0xf8 0xe4 0x30
Convert the uses of '\|&' to use '2>&1 \|' instead, which works on old versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159544 91177308-0d34-0410-b5e6-96231b3b80d8 2012-07-02 18:37:59 +00:00			`# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 \| FileCheck %s`
ARM disassembler was erroneously accepting an invalid RSC instruction. Added checks for regs which should not be 15. rdar://problem/9237734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-05 22:18:07 +00:00
			`# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)`
Tighten operand checking of register-shifted-register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8 2011-08-09 23:33:27 +00:00			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
ARM disassembler was erroneously accepting an invalid RSC instruction. Added checks for regs which should not be 15. rdar://problem/9237734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-05 22:18:07 +00:00			`# -------------------------------------------------------------------------------------------------`
			`# \| 0: 0: 1: 1\| 0: 0: 0: 0\| 1: 1: 1: 0\| 0: 1: 0: 0\| 1: 1: 1: 1\| 1: 0: 0: 0\| 0: 1: 0: 1\| 1: 1: 1: 1\|`
			`# -------------------------------------------------------------------------------------------------`
			`# if d == 15 \|\| n == 15 \|\| m == 15 \|\| s == 15 then UNPREDICTABLE;`
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8 2012-03-20 15:54:56 +00:00
			`# CHECK: warning: potentially undefined instruction encoding`
ARM disassembler was erroneously accepting an invalid RSC instruction. Added checks for regs which should not be 15. rdar://problem/9237734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-05 22:18:07 +00:00			`0x5f 0xf8 0xe4 0x30`