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https://github.com/c64scene-ar/llvm-6502.git
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32 lines
951 B
LLVM
32 lines
951 B
LLVM
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; RUN: llc < %s -O3 -march=aarch64 -mcpu=cortex-a53 | FileCheck %s
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; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the
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; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down
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; post-RA MI scheduler will clean this up.
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@d1 = common global double 0.000000e+00, align 8
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define i32 @test1(float %s2, float %s3, double %d, i32 %i2, i32 %i3) {
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entry:
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; CHECK-LABEL: @test1
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; CHECK: fmul
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; CHECK-NEXT: add
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; CHECK: fcvt
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; CHECK-NEXT: mul
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%mul = fmul float %s2, %s3
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%conv = fpext float %mul to double
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%div = fdiv double %d, %conv
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store double %div, double* @d1, align 8
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%factor = shl i32 %i3, 1
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%add1 = add i32 %i2, 4
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%add2 = add i32 %add1, %factor
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%add3 = add nsw i32 %add2, %i2
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%add4 = add nsw i32 %add3, %add2
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%mul5 = mul i32 %add3, %add3
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%mul6 = mul i32 %mul5, %add4
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%mul7 = shl i32 %add4, 1
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%factor18 = mul i32 %mul7, %mul6
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%add9 = add i32 %factor18, %mul6
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ret i32 %add9
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}
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