2011-02-17 19:18:59 +00:00
|
|
|
//===-- X86ShuffleDecode.h - X86 shuffle decode logic -----------*-C++-*---===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// Define several functions to decode x86 specific shuffle semantics into a
|
|
|
|
// generic vector mask.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef X86_SHUFFLE_DECODE_H
|
|
|
|
#define X86_SHUFFLE_DECODE_H
|
|
|
|
|
|
|
|
#include "llvm/ADT/SmallVector.h"
|
2011-02-28 19:06:56 +00:00
|
|
|
#include "llvm/CodeGen/ValueTypes.h"
|
2011-02-17 19:18:59 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Vector Mask Decoding
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
enum {
|
|
|
|
SM_SentinelZero = ~0U
|
|
|
|
};
|
|
|
|
|
|
|
|
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
// <3,1> or <6,7,2,3>
|
|
|
|
void DecodeMOVHLPSMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
// <0,2> or <0,1,4,5>
|
|
|
|
void DecodeMOVLHPSMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePSHUFMask(unsigned NElts, unsigned Imm,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePSHUFHWMask(unsigned Imm,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePSHUFLWMask(unsigned Imm,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
2011-02-28 19:06:56 +00:00
|
|
|
void DecodePUNPCKLBWMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePUNPCKLWDMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePUNPCKLDQMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePUNPCKLQDQMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePUNPCKLMask(EVT VT,
|
2011-02-17 19:18:59 +00:00
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodePUNPCKHMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodeSHUFPSMask(unsigned NElts, unsigned Imm,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodeUNPCKHPMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
2011-02-28 19:06:56 +00:00
|
|
|
void DecodeUNPCKLPSMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
|
|
|
void DecodeUNPCKLPDMask(unsigned NElts,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
2011-02-17 19:18:59 +00:00
|
|
|
|
|
|
|
/// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd
|
2011-02-28 19:06:56 +00:00
|
|
|
/// etc. VT indicates the type of the vector allowing it to handle different
|
|
|
|
/// datatypes and vector widths.
|
|
|
|
void DecodeUNPCKLPMask(EVT VT,
|
2011-02-17 19:18:59 +00:00
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
|
|
|
|
2011-07-29 01:31:11 +00:00
|
|
|
// DecodeVPERMILPSMask - Decodes VPERMILPS permutes for any 128-bit 32-bit
|
|
|
|
// elements. For 256-bit vectors, it's considered as two 128 lanes, the
|
|
|
|
// referenced elements can't cross lanes and the mask of the first lane must
|
|
|
|
// be the same of the second.
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
|
|
|
void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
2011-07-29 01:31:11 +00:00
|
|
|
// DecodeVPERMILPDMask - Decodes VPERMILPD permutes for any 128-bit 64-bit
|
|
|
|
// elements. For 256-bit vectors, it's considered as two 128 lanes, the
|
|
|
|
// referenced elements can't cross lanes but the mask of the first lane can
|
|
|
|
// be the different of the second (not like VPERMILPS).
|
Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
|
|
|
void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
|
|
|
|
SmallVectorImpl<unsigned> &ShuffleMask);
|
|
|
|
|
2011-02-17 19:18:59 +00:00
|
|
|
} // llvm namespace
|
|
|
|
|
|
|
|
#endif
|