2002-12-28 20:43:30 +00:00
|
|
|
//===-- PrologEpilogInserter.cpp - Insert Prolog/Epilog code in function --===//
|
2005-04-21 22:36:52 +00:00
|
|
|
//
|
2003-10-20 19:43:21 +00:00
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2005-04-21 22:36:52 +00:00
|
|
|
//
|
2003-10-20 19:43:21 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2002-12-28 20:43:30 +00:00
|
|
|
//
|
|
|
|
// This pass is responsible for finalizing the functions frame layout, saving
|
|
|
|
// callee saved registers, and for emitting prolog & epilog code for the
|
|
|
|
// function.
|
|
|
|
//
|
|
|
|
// This pass must be run after register allocation. After this pass is
|
|
|
|
// executed, it is illegal to construct MO_FrameIndex operands.
|
|
|
|
//
|
2009-05-12 20:33:29 +00:00
|
|
|
// This pass provides an optional shrink wrapping variant of prolog/epilog
|
|
|
|
// insertion, enabled via --shrink-wrap. See ShrinkWrapping.cpp.
|
2009-03-27 06:09:40 +00:00
|
|
|
//
|
2002-12-28 20:43:30 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2009-05-13 17:52:11 +00:00
|
|
|
#include "PrologEpilogInserter.h"
|
2009-03-27 06:09:40 +00:00
|
|
|
#include "llvm/CodeGen/MachineDominators.h"
|
|
|
|
#include "llvm/CodeGen/MachineLoopInfo.h"
|
2002-12-28 20:43:30 +00:00
|
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
2002-12-28 21:08:26 +00:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2007-12-31 04:13:23 +00:00
|
|
|
#include "llvm/CodeGen/MachineModuleInfo.h"
|
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2007-02-23 01:11:26 +00:00
|
|
|
#include "llvm/CodeGen/RegisterScavenging.h"
|
2002-12-28 20:43:30 +00:00
|
|
|
#include "llvm/Target/TargetMachine.h"
|
2008-02-10 18:45:23 +00:00
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
2002-12-28 21:00:25 +00:00
|
|
|
#include "llvm/Target/TargetFrameInfo.h"
|
2003-01-14 22:00:31 +00:00
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2006-08-27 12:54:02 +00:00
|
|
|
#include "llvm/Support/Compiler.h"
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
#include "llvm/ADT/IndexedMap.h"
|
2007-05-01 09:01:42 +00:00
|
|
|
#include "llvm/ADT/STLExtras.h"
|
2006-09-28 00:10:27 +00:00
|
|
|
#include <climits>
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2004-02-15 00:14:20 +00:00
|
|
|
using namespace llvm;
|
2003-11-11 22:41:34 +00:00
|
|
|
|
2009-05-12 20:33:29 +00:00
|
|
|
char PEI::ID = 0;
|
2009-05-11 17:04:19 +00:00
|
|
|
|
2009-05-12 20:33:29 +00:00
|
|
|
static RegisterPass<PEI>
|
|
|
|
X("prologepilog", "Prologue/Epilogue Insertion");
|
2009-05-11 17:04:19 +00:00
|
|
|
|
2002-12-28 20:43:30 +00:00
|
|
|
/// createPrologEpilogCodeInserter - This function returns a pass that inserts
|
|
|
|
/// prolog and epilog code, and eliminates abstract frame references.
|
|
|
|
///
|
2004-02-15 00:14:20 +00:00
|
|
|
FunctionPass *llvm::createPrologEpilogCodeInserter() { return new PEI(); }
|
2002-12-28 20:43:30 +00:00
|
|
|
|
2009-05-12 20:33:29 +00:00
|
|
|
/// runOnMachineFunction - Insert prolog/epilog code and replace abstract
|
|
|
|
/// frame indexes with appropriate references.
|
2009-05-11 17:04:19 +00:00
|
|
|
///
|
2009-05-12 20:33:29 +00:00
|
|
|
bool PEI::runOnMachineFunction(MachineFunction &Fn) {
|
2009-07-17 18:07:26 +00:00
|
|
|
const Function* F = Fn.getFunction();
|
2009-05-11 17:04:19 +00:00
|
|
|
const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
|
2009-05-12 20:33:29 +00:00
|
|
|
RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
|
2009-10-08 01:46:59 +00:00
|
|
|
FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
|
2009-05-12 20:33:29 +00:00
|
|
|
|
|
|
|
// Get MachineModuleInfo so that we can track the construction of the
|
|
|
|
// frame.
|
|
|
|
if (MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>())
|
|
|
|
Fn.getFrameInfo()->setMachineModuleInfo(MMI);
|
|
|
|
|
2009-07-16 13:50:40 +00:00
|
|
|
// Calculate the MaxCallFrameSize and HasCalls variables for the function's
|
|
|
|
// frame information. Also eliminates call frame pseudo instructions.
|
|
|
|
calculateCallsInformation(Fn);
|
|
|
|
|
2009-05-12 20:33:29 +00:00
|
|
|
// Allow the target machine to make some adjustments to the function
|
|
|
|
// e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
|
|
|
|
TRI->processFunctionBeforeCalleeSavedScan(Fn, RS);
|
|
|
|
|
2009-07-16 13:50:40 +00:00
|
|
|
// Scan the function for modified callee saved registers and insert spill code
|
|
|
|
// for any callee saved registers that are modified.
|
2009-05-12 20:33:29 +00:00
|
|
|
calculateCalleeSavedRegisters(Fn);
|
|
|
|
|
|
|
|
// Determine placement of CSR spill/restore code:
|
|
|
|
// - with shrink wrapping, place spills and restores to tightly
|
|
|
|
// enclose regions in the Machine CFG of the function where
|
|
|
|
// they are used. Without shrink wrapping
|
|
|
|
// - default (no shrink wrapping), place all spills in the
|
|
|
|
// entry block, all restores in return blocks.
|
|
|
|
placeCSRSpillsAndRestores(Fn);
|
|
|
|
|
|
|
|
// Add the code to save and restore the callee saved registers
|
2009-07-17 18:07:26 +00:00
|
|
|
if (!F->hasFnAttr(Attribute::Naked))
|
|
|
|
insertCSRSpillsAndRestores(Fn);
|
2009-05-12 20:33:29 +00:00
|
|
|
|
|
|
|
// Allow the target machine to make final modifications to the function
|
|
|
|
// before the frame layout is finalized.
|
|
|
|
TRI->processFunctionBeforeFrameFinalized(Fn);
|
|
|
|
|
|
|
|
// Calculate actual frame offsets for all abstract stack objects...
|
|
|
|
calculateFrameObjectOffsets(Fn);
|
|
|
|
|
|
|
|
// Add prolog and epilog code to the function. This function is required
|
|
|
|
// to align the stack frame as necessary for any stack variables or
|
|
|
|
// called functions. Because of this, calculateCalleeSavedRegisters
|
|
|
|
// must be called before this function in order to set the HasCalls
|
|
|
|
// and MaxCallFrameSize variables.
|
2009-07-17 18:07:26 +00:00
|
|
|
if (!F->hasFnAttr(Attribute::Naked))
|
|
|
|
insertPrologEpilogCode(Fn);
|
2009-05-12 20:33:29 +00:00
|
|
|
|
|
|
|
// Replace all MO_FrameIndex operands with physical register references
|
|
|
|
// and actual offsets.
|
|
|
|
//
|
|
|
|
replaceFrameIndices(Fn);
|
2009-05-11 17:04:19 +00:00
|
|
|
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
// If register scavenging is needed, as we've enabled doing it as a
|
|
|
|
// post-pass, scavenge the virtual registers that frame index elimiation
|
|
|
|
// inserted.
|
|
|
|
if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
|
|
|
|
scavengeFrameVirtualRegs(Fn);
|
|
|
|
|
2009-05-12 20:33:29 +00:00
|
|
|
delete RS;
|
|
|
|
clearAllSets();
|
2009-05-11 17:04:19 +00:00
|
|
|
return true;
|
2009-03-27 06:09:40 +00:00
|
|
|
}
|
|
|
|
|
2009-05-12 20:33:29 +00:00
|
|
|
#if 0
|
|
|
|
void PEI::getAnalysisUsage(AnalysisUsage &AU) const {
|
2009-07-31 23:37:33 +00:00
|
|
|
AU.setPreservesCFG();
|
2009-05-12 20:33:29 +00:00
|
|
|
if (ShrinkWrapping || ShrinkWrapFunc != "") {
|
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
AU.addRequired<MachineDominatorTree>();
|
2009-05-11 17:04:19 +00:00
|
|
|
}
|
2009-05-12 20:33:29 +00:00
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
2009-03-27 06:09:40 +00:00
|
|
|
}
|
2009-05-12 20:33:29 +00:00
|
|
|
#endif
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2009-07-16 13:50:40 +00:00
|
|
|
/// calculateCallsInformation - Calculate the MaxCallFrameSize and HasCalls
|
|
|
|
/// variables for the function's frame information and eliminate call frame
|
|
|
|
/// pseudo instructions.
|
|
|
|
void PEI::calculateCallsInformation(MachineFunction &Fn) {
|
2008-02-10 18:45:23 +00:00
|
|
|
const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
|
2009-12-11 19:39:55 +00:00
|
|
|
MachineFrameInfo *FFI = Fn.getFrameInfo();
|
2002-12-28 20:43:30 +00:00
|
|
|
|
2009-07-16 13:50:40 +00:00
|
|
|
unsigned MaxCallFrameSize = 0;
|
2009-12-11 19:39:55 +00:00
|
|
|
bool HasCalls = FFI->hasCalls();
|
2002-12-28 20:43:30 +00:00
|
|
|
|
|
|
|
// Get the function call frame set-up and tear-down instruction opcode
|
|
|
|
int FrameSetupOpcode = RegInfo->getCallFrameSetupOpcode();
|
|
|
|
int FrameDestroyOpcode = RegInfo->getCallFrameDestroyOpcode();
|
|
|
|
|
2009-07-16 13:50:40 +00:00
|
|
|
// Early exit for targets which have no call frame setup/destroy pseudo
|
|
|
|
// instructions.
|
|
|
|
if (FrameSetupOpcode == -1 && FrameDestroyOpcode == -1)
|
2002-12-28 20:43:30 +00:00
|
|
|
return;
|
|
|
|
|
2007-05-01 00:52:08 +00:00
|
|
|
std::vector<MachineBasicBlock::iterator> FrameSDOps;
|
2002-12-28 20:43:30 +00:00
|
|
|
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
|
2007-05-01 00:52:08 +00:00
|
|
|
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
|
2004-02-12 02:27:10 +00:00
|
|
|
if (I->getOpcode() == FrameSetupOpcode ||
|
2004-08-07 07:07:57 +00:00
|
|
|
I->getOpcode() == FrameDestroyOpcode) {
|
2005-05-13 21:07:15 +00:00
|
|
|
assert(I->getNumOperands() >= 1 && "Call Frame Setup/Destroy Pseudo"
|
2004-08-07 07:07:57 +00:00
|
|
|
" instructions should have a single immediate argument!");
|
2007-12-30 20:50:28 +00:00
|
|
|
unsigned Size = I->getOperand(0).getImm();
|
2004-08-07 07:07:57 +00:00
|
|
|
if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
|
|
|
|
HasCalls = true;
|
2007-05-01 00:52:08 +00:00
|
|
|
FrameSDOps.push_back(I);
|
2009-07-16 22:34:45 +00:00
|
|
|
} else if (I->getOpcode() == TargetInstrInfo::INLINEASM) {
|
|
|
|
// An InlineAsm might be a call; assume it is to get the stack frame
|
|
|
|
// aligned correctly for calls.
|
|
|
|
HasCalls = true;
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
FFI->setHasCalls(HasCalls);
|
|
|
|
FFI->setMaxCallFrameSize(MaxCallFrameSize);
|
2007-05-01 09:01:42 +00:00
|
|
|
|
2009-07-08 20:57:27 +00:00
|
|
|
for (std::vector<MachineBasicBlock::iterator>::iterator
|
|
|
|
i = FrameSDOps.begin(), e = FrameSDOps.end(); i != e; ++i) {
|
|
|
|
MachineBasicBlock::iterator I = *i;
|
|
|
|
|
|
|
|
// If call frames are not being included as part of the stack frame, and
|
|
|
|
// there is no dynamic allocation (therefore referencing frame slots off
|
|
|
|
// sp), leave the pseudo ops alone. We'll eliminate them later.
|
2007-05-01 09:01:42 +00:00
|
|
|
if (RegInfo->hasReservedCallFrame(Fn) || RegInfo->hasFP(Fn))
|
|
|
|
RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
|
2007-05-01 00:52:08 +00:00
|
|
|
}
|
2009-07-16 13:50:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// calculateCalleeSavedRegisters - Scan the function for modified callee saved
|
|
|
|
/// registers.
|
|
|
|
void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
|
|
|
|
const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
|
|
|
|
const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
|
|
|
|
MachineFrameInfo *FFI = Fn.getFrameInfo();
|
|
|
|
|
|
|
|
// Get the callee saved register list...
|
|
|
|
const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(&Fn);
|
|
|
|
|
|
|
|
// These are used to keep track the callee-save area. Initialize them.
|
|
|
|
MinCSFrameIndex = INT_MAX;
|
|
|
|
MaxCSFrameIndex = 0;
|
|
|
|
|
|
|
|
// Early exit for targets which have no callee saved registers.
|
|
|
|
if (CSRegs == 0 || CSRegs[0] == 0)
|
|
|
|
return;
|
2002-12-28 20:43:30 +00:00
|
|
|
|
2009-07-16 13:50:40 +00:00
|
|
|
// Figure out which *callee saved* registers are modified by the current
|
2002-12-28 20:43:30 +00:00
|
|
|
// function, thus needing to be saved and restored in the prolog/epilog.
|
2009-07-08 20:57:27 +00:00
|
|
|
const TargetRegisterClass * const *CSRegClasses =
|
2007-07-14 14:06:15 +00:00
|
|
|
RegInfo->getCalleeSavedRegClasses(&Fn);
|
2009-07-08 20:57:27 +00:00
|
|
|
|
2006-08-25 22:56:30 +00:00
|
|
|
std::vector<CalleeSavedInfo> CSI;
|
2002-12-28 20:43:30 +00:00
|
|
|
for (unsigned i = 0; CSRegs[i]; ++i) {
|
|
|
|
unsigned Reg = CSRegs[i];
|
2009-05-13 23:50:53 +00:00
|
|
|
if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
|
2009-07-08 20:57:27 +00:00
|
|
|
// If the reg is modified, save it!
|
2006-08-25 19:45:51 +00:00
|
|
|
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
|
2003-10-08 05:20:08 +00:00
|
|
|
} else {
|
|
|
|
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
|
2005-01-23 23:13:12 +00:00
|
|
|
*AliasSet; ++AliasSet) { // Check alias registers too.
|
2007-12-31 04:13:23 +00:00
|
|
|
if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) {
|
2006-08-25 19:45:51 +00:00
|
|
|
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
|
2004-08-07 07:07:57 +00:00
|
|
|
break;
|
2004-08-07 07:18:41 +00:00
|
|
|
}
|
2003-10-08 05:20:08 +00:00
|
|
|
}
|
|
|
|
}
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
|
|
|
|
2006-08-25 19:45:51 +00:00
|
|
|
if (CSI.empty())
|
2006-09-28 00:10:27 +00:00
|
|
|
return; // Early exit if no callee saved registers are modified!
|
2002-12-28 20:43:30 +00:00
|
|
|
|
2004-08-12 19:01:14 +00:00
|
|
|
unsigned NumFixedSpillSlots;
|
2009-09-27 17:58:47 +00:00
|
|
|
const TargetFrameInfo::SpillSlot *FixedSpillSlots =
|
2007-01-02 21:31:15 +00:00
|
|
|
TFI->getCalleeSavedSpillSlots(NumFixedSpillSlots);
|
2004-08-12 19:01:14 +00:00
|
|
|
|
2002-12-28 20:43:30 +00:00
|
|
|
// Now that we know which registers need to be saved and restored, allocate
|
|
|
|
// stack slots for them.
|
2009-07-08 20:57:27 +00:00
|
|
|
for (std::vector<CalleeSavedInfo>::iterator
|
|
|
|
I = CSI.begin(), E = CSI.end(); I != E; ++I) {
|
|
|
|
unsigned Reg = I->getReg();
|
|
|
|
const TargetRegisterClass *RC = I->getRegClass();
|
2004-08-12 19:01:14 +00:00
|
|
|
|
2009-07-09 06:53:48 +00:00
|
|
|
int FrameIdx;
|
|
|
|
if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) {
|
|
|
|
I->setFrameIdx(FrameIdx);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2004-08-12 19:01:14 +00:00
|
|
|
// Check to see if this physreg must be spilled to a particular stack slot
|
|
|
|
// on this target.
|
2009-09-27 17:58:47 +00:00
|
|
|
const TargetFrameInfo::SpillSlot *FixedSlot = FixedSpillSlots;
|
2004-08-12 19:01:14 +00:00
|
|
|
while (FixedSlot != FixedSpillSlots+NumFixedSpillSlots &&
|
2009-09-27 17:58:47 +00:00
|
|
|
FixedSlot->Reg != Reg)
|
2004-08-12 19:01:14 +00:00
|
|
|
++FixedSlot;
|
|
|
|
|
2009-07-08 20:57:27 +00:00
|
|
|
if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) {
|
2004-08-12 19:01:14 +00:00
|
|
|
// Nope, just spill it anywhere convenient.
|
2006-09-28 18:52:32 +00:00
|
|
|
unsigned Align = RC->getAlignment();
|
|
|
|
unsigned StackAlign = TFI->getStackAlignment();
|
2009-07-08 20:57:27 +00:00
|
|
|
|
|
|
|
// We may not be able to satisfy the desired alignment specification of
|
|
|
|
// the TargetRegisterClass if the stack alignment is smaller. Use the
|
|
|
|
// min.
|
2006-09-28 18:52:32 +00:00
|
|
|
Align = std::min(Align, StackAlign);
|
2009-10-17 09:20:14 +00:00
|
|
|
FrameIdx = FFI->CreateStackObject(RC->getSize(), Align, true);
|
2006-09-28 00:10:27 +00:00
|
|
|
if ((unsigned)FrameIdx < MinCSFrameIndex) MinCSFrameIndex = FrameIdx;
|
|
|
|
if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
|
2004-08-12 19:01:14 +00:00
|
|
|
} else {
|
|
|
|
// Spill it to the stack where we must.
|
2009-11-12 20:49:22 +00:00
|
|
|
FrameIdx = FFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset,
|
|
|
|
true, false);
|
2004-08-12 19:01:14 +00:00
|
|
|
}
|
2009-07-08 20:57:27 +00:00
|
|
|
|
|
|
|
I->setFrameIdx(FrameIdx);
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
2006-08-25 22:56:30 +00:00
|
|
|
|
|
|
|
FFI->setCalleeSavedInfo(CSI);
|
2004-08-12 19:01:14 +00:00
|
|
|
}
|
|
|
|
|
2009-03-27 06:09:40 +00:00
|
|
|
/// insertCSRSpillsAndRestores - Insert spill and restore code for
|
|
|
|
/// callee saved registers used in the function, handling shrink wrapping.
|
2004-08-12 19:01:14 +00:00
|
|
|
///
|
2009-03-27 06:09:40 +00:00
|
|
|
void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
|
2006-08-25 19:45:51 +00:00
|
|
|
// Get callee saved register information.
|
|
|
|
MachineFrameInfo *FFI = Fn.getFrameInfo();
|
2006-08-25 22:56:30 +00:00
|
|
|
const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2009-08-15 13:10:46 +00:00
|
|
|
FFI->setCalleeSavedInfoValid(true);
|
|
|
|
|
2006-09-28 00:10:27 +00:00
|
|
|
// Early exit if no callee saved registers are modified!
|
2006-08-25 19:45:51 +00:00
|
|
|
if (CSI.empty())
|
2005-04-21 22:36:52 +00:00
|
|
|
return;
|
2004-08-12 19:01:14 +00:00
|
|
|
|
2008-01-01 21:11:32 +00:00
|
|
|
const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
|
2009-03-27 06:09:40 +00:00
|
|
|
MachineBasicBlock::iterator I;
|
2008-01-31 00:27:49 +00:00
|
|
|
|
2009-05-11 17:04:19 +00:00
|
|
|
if (! ShrinkWrapThisFunction) {
|
|
|
|
// Spill using target interface.
|
|
|
|
I = EntryBlock->begin();
|
|
|
|
if (!TII.spillCalleeSavedRegisters(*EntryBlock, I, CSI)) {
|
|
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
2009-03-27 06:09:40 +00:00
|
|
|
// Add the callee-saved register as live-in.
|
|
|
|
// It's killed at the spill.
|
2009-05-11 17:04:19 +00:00
|
|
|
EntryBlock->addLiveIn(CSI[i].getReg());
|
2009-03-27 06:09:40 +00:00
|
|
|
|
|
|
|
// Insert the spill to the stack frame.
|
2009-05-11 17:04:19 +00:00
|
|
|
TII.storeRegToStackSlot(*EntryBlock, I, CSI[i].getReg(), true,
|
|
|
|
CSI[i].getFrameIdx(), CSI[i].getRegClass());
|
2009-03-27 06:09:40 +00:00
|
|
|
}
|
2007-01-02 21:31:15 +00:00
|
|
|
}
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2009-05-11 17:04:19 +00:00
|
|
|
// Restore using target interface.
|
|
|
|
for (unsigned ri = 0, re = ReturnBlocks.size(); ri != re; ++ri) {
|
|
|
|
MachineBasicBlock* MBB = ReturnBlocks[ri];
|
2004-02-12 02:27:10 +00:00
|
|
|
I = MBB->end(); --I;
|
2002-12-28 20:43:30 +00:00
|
|
|
|
2008-10-31 18:30:19 +00:00
|
|
|
// Skip over all terminator instructions, which are part of the return
|
2005-05-15 03:09:58 +00:00
|
|
|
// sequence.
|
|
|
|
MachineBasicBlock::iterator I2 = I;
|
2008-10-31 18:30:19 +00:00
|
|
|
while (I2 != MBB->begin() && (--I2)->getDesc().isTerminator())
|
2005-05-15 03:09:58 +00:00
|
|
|
I = I2;
|
|
|
|
|
2005-08-29 00:10:46 +00:00
|
|
|
bool AtStart = I == MBB->begin();
|
2005-08-26 22:18:32 +00:00
|
|
|
MachineBasicBlock::iterator BeforeI = I;
|
|
|
|
if (!AtStart)
|
|
|
|
--BeforeI;
|
2009-03-27 06:09:40 +00:00
|
|
|
|
|
|
|
// Restore all registers immediately before the return and any
|
|
|
|
// terminators that preceed it.
|
2008-01-05 00:48:55 +00:00
|
|
|
if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI)) {
|
2007-01-02 21:31:15 +00:00
|
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
2008-01-01 21:11:32 +00:00
|
|
|
TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
|
2009-03-27 06:09:40 +00:00
|
|
|
CSI[i].getFrameIdx(),
|
|
|
|
CSI[i].getRegClass());
|
2007-01-02 21:31:15 +00:00
|
|
|
assert(I != MBB->begin() &&
|
|
|
|
"loadRegFromStackSlot didn't insert any code!");
|
2009-03-27 06:09:40 +00:00
|
|
|
// Insert in reverse order. loadRegFromStackSlot can insert
|
|
|
|
// multiple instructions.
|
2007-01-02 21:31:15 +00:00
|
|
|
if (AtStart)
|
|
|
|
I = MBB->begin();
|
|
|
|
else {
|
|
|
|
I = BeforeI;
|
|
|
|
++I;
|
|
|
|
}
|
2005-08-26 22:18:32 +00:00
|
|
|
}
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
2009-05-11 17:04:19 +00:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2009-05-11 17:04:19 +00:00
|
|
|
// Insert spills.
|
|
|
|
std::vector<CalleeSavedInfo> blockCSI;
|
|
|
|
for (CSRegBlockMap::iterator BI = CSRSave.begin(),
|
|
|
|
BE = CSRSave.end(); BI != BE; ++BI) {
|
|
|
|
MachineBasicBlock* MBB = BI->first;
|
|
|
|
CSRegSet save = BI->second;
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2009-05-11 17:04:19 +00:00
|
|
|
if (save.empty())
|
|
|
|
continue;
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2009-05-11 17:04:19 +00:00
|
|
|
blockCSI.clear();
|
|
|
|
for (CSRegSet::iterator RI = save.begin(),
|
|
|
|
RE = save.end(); RI != RE; ++RI) {
|
|
|
|
blockCSI.push_back(CSI[*RI]);
|
|
|
|
}
|
|
|
|
assert(blockCSI.size() > 0 &&
|
|
|
|
"Could not collect callee saved register info");
|
|
|
|
|
|
|
|
I = MBB->begin();
|
|
|
|
|
|
|
|
// When shrink wrapping, use stack slot stores/loads.
|
|
|
|
for (unsigned i = 0, e = blockCSI.size(); i != e; ++i) {
|
|
|
|
// Add the callee-saved register as live-in.
|
|
|
|
// It's killed at the spill.
|
|
|
|
MBB->addLiveIn(blockCSI[i].getReg());
|
|
|
|
|
|
|
|
// Insert the spill to the stack frame.
|
|
|
|
TII.storeRegToStackSlot(*MBB, I, blockCSI[i].getReg(),
|
|
|
|
true,
|
|
|
|
blockCSI[i].getFrameIdx(),
|
|
|
|
blockCSI[i].getRegClass());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (CSRegBlockMap::iterator BI = CSRRestore.begin(),
|
|
|
|
BE = CSRRestore.end(); BI != BE; ++BI) {
|
|
|
|
MachineBasicBlock* MBB = BI->first;
|
|
|
|
CSRegSet restore = BI->second;
|
|
|
|
|
|
|
|
if (restore.empty())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
blockCSI.clear();
|
|
|
|
for (CSRegSet::iterator RI = restore.begin(),
|
|
|
|
RE = restore.end(); RI != RE; ++RI) {
|
|
|
|
blockCSI.push_back(CSI[*RI]);
|
|
|
|
}
|
|
|
|
assert(blockCSI.size() > 0 &&
|
|
|
|
"Could not find callee saved register info");
|
|
|
|
|
|
|
|
// If MBB is empty and needs restores, insert at the _beginning_.
|
|
|
|
if (MBB->empty()) {
|
|
|
|
I = MBB->begin();
|
|
|
|
} else {
|
|
|
|
I = MBB->end();
|
|
|
|
--I;
|
|
|
|
|
|
|
|
// Skip over all terminator instructions, which are part of the
|
|
|
|
// return sequence.
|
|
|
|
if (! I->getDesc().isTerminator()) {
|
|
|
|
++I;
|
2009-03-27 06:09:40 +00:00
|
|
|
} else {
|
2009-05-11 17:04:19 +00:00
|
|
|
MachineBasicBlock::iterator I2 = I;
|
|
|
|
while (I2 != MBB->begin() && (--I2)->getDesc().isTerminator())
|
|
|
|
I = I2;
|
2009-03-27 06:09:40 +00:00
|
|
|
}
|
2009-05-11 17:04:19 +00:00
|
|
|
}
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2009-05-11 17:04:19 +00:00
|
|
|
bool AtStart = I == MBB->begin();
|
|
|
|
MachineBasicBlock::iterator BeforeI = I;
|
|
|
|
if (!AtStart)
|
|
|
|
--BeforeI;
|
|
|
|
|
|
|
|
// Restore all registers immediately before the return and any
|
|
|
|
// terminators that preceed it.
|
|
|
|
for (unsigned i = 0, e = blockCSI.size(); i != e; ++i) {
|
|
|
|
TII.loadRegFromStackSlot(*MBB, I, blockCSI[i].getReg(),
|
|
|
|
blockCSI[i].getFrameIdx(),
|
|
|
|
blockCSI[i].getRegClass());
|
|
|
|
assert(I != MBB->begin() &&
|
|
|
|
"loadRegFromStackSlot didn't insert any code!");
|
|
|
|
// Insert in reverse order. loadRegFromStackSlot can insert
|
|
|
|
// multiple instructions.
|
|
|
|
if (AtStart)
|
|
|
|
I = MBB->begin();
|
|
|
|
else {
|
|
|
|
I = BeforeI;
|
|
|
|
++I;
|
2009-03-27 06:09:40 +00:00
|
|
|
}
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
2009-03-27 06:09:40 +00:00
|
|
|
}
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
|
|
|
|
2008-11-07 01:48:58 +00:00
|
|
|
/// AdjustStackOffset - Helper function used to adjust the stack frame offset.
|
|
|
|
static inline void
|
|
|
|
AdjustStackOffset(MachineFrameInfo *FFI, int FrameIdx,
|
|
|
|
bool StackGrowsDown, int64_t &Offset,
|
|
|
|
unsigned &MaxAlign) {
|
2009-09-23 18:53:19 +00:00
|
|
|
// If the stack grows down, add the object size to find the lowest address.
|
2008-11-07 01:48:58 +00:00
|
|
|
if (StackGrowsDown)
|
|
|
|
Offset += FFI->getObjectSize(FrameIdx);
|
|
|
|
|
|
|
|
unsigned Align = FFI->getObjectAlignment(FrameIdx);
|
|
|
|
|
|
|
|
// If the alignment of this object is greater than that of the stack, then
|
|
|
|
// increase the stack alignment to match.
|
|
|
|
MaxAlign = std::max(MaxAlign, Align);
|
|
|
|
|
|
|
|
// Adjust to alignment boundary.
|
|
|
|
Offset = (Offset + Align - 1) / Align * Align;
|
|
|
|
|
|
|
|
if (StackGrowsDown) {
|
|
|
|
FFI->setObjectOffset(FrameIdx, -Offset); // Set the computed offset
|
|
|
|
} else {
|
|
|
|
FFI->setObjectOffset(FrameIdx, Offset);
|
|
|
|
Offset += FFI->getObjectSize(FrameIdx);
|
|
|
|
}
|
|
|
|
}
|
2002-12-28 20:43:30 +00:00
|
|
|
|
|
|
|
/// calculateFrameObjectOffsets - Calculate actual frame offsets for all of the
|
2005-01-23 21:45:01 +00:00
|
|
|
/// abstract stack objects.
|
2002-12-28 20:43:30 +00:00
|
|
|
///
|
|
|
|
void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
|
2004-06-02 05:57:12 +00:00
|
|
|
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2002-12-28 20:43:30 +00:00
|
|
|
bool StackGrowsDown =
|
|
|
|
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2002-12-28 20:43:30 +00:00
|
|
|
// Loop over all of the stack objects, assigning sequential addresses...
|
2002-12-28 21:08:26 +00:00
|
|
|
MachineFrameInfo *FFI = Fn.getFrameInfo();
|
2002-12-28 20:43:30 +00:00
|
|
|
|
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
|
|
|
unsigned MaxAlign = 1;
|
2003-01-16 02:22:08 +00:00
|
|
|
|
2004-02-15 00:14:20 +00:00
|
|
|
// Start at the beginning of the local area.
|
2004-06-10 06:23:35 +00:00
|
|
|
// The Offset is the distance from the stack top in the direction
|
2008-07-16 15:57:10 +00:00
|
|
|
// of stack growth -- so it's always nonnegative.
|
2009-09-24 16:42:27 +00:00
|
|
|
int LocalAreaOffset = TFI.getOffsetOfLocalArea();
|
2004-06-10 06:23:35 +00:00
|
|
|
if (StackGrowsDown)
|
2009-09-24 16:42:27 +00:00
|
|
|
LocalAreaOffset = -LocalAreaOffset;
|
|
|
|
assert(LocalAreaOffset >= 0
|
2004-06-10 06:23:35 +00:00
|
|
|
&& "Local area offset should be in direction of stack growth");
|
2009-09-24 16:42:27 +00:00
|
|
|
int64_t Offset = LocalAreaOffset;
|
2004-06-10 06:23:35 +00:00
|
|
|
|
|
|
|
// If there are fixed sized objects that are preallocated in the local area,
|
|
|
|
// non-fixed objects can't be allocated right at the start of local area.
|
2009-03-27 06:09:40 +00:00
|
|
|
// We currently don't support filling in holes in between fixed sized
|
|
|
|
// objects, so we adjust 'Offset' to point to the end of last fixed sized
|
2004-02-15 00:14:20 +00:00
|
|
|
// preallocated object.
|
|
|
|
for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
|
2007-04-25 04:20:54 +00:00
|
|
|
int64_t FixedOff;
|
2004-06-10 06:23:35 +00:00
|
|
|
if (StackGrowsDown) {
|
|
|
|
// The maximum distance from the stack pointer is at lower address of
|
|
|
|
// the object -- which is given by offset. For down growing stack
|
|
|
|
// the offset is negative, so we negate the offset to get the distance.
|
|
|
|
FixedOff = -FFI->getObjectOffset(i);
|
|
|
|
} else {
|
2005-04-21 22:36:52 +00:00
|
|
|
// The maximum distance from the start pointer is at the upper
|
2004-06-10 06:23:35 +00:00
|
|
|
// address of the object.
|
|
|
|
FixedOff = FFI->getObjectOffset(i) + FFI->getObjectSize(i);
|
2005-04-21 22:36:52 +00:00
|
|
|
}
|
|
|
|
if (FixedOff > Offset) Offset = FixedOff;
|
2004-02-15 00:14:20 +00:00
|
|
|
}
|
|
|
|
|
2006-09-28 00:10:27 +00:00
|
|
|
// First assign frame offsets to stack objects that are used to spill
|
2007-01-02 21:31:15 +00:00
|
|
|
// callee saved registers.
|
2006-09-28 00:10:27 +00:00
|
|
|
if (StackGrowsDown) {
|
2007-05-01 00:52:08 +00:00
|
|
|
for (unsigned i = MinCSFrameIndex; i <= MaxCSFrameIndex; ++i) {
|
2006-09-28 00:10:27 +00:00
|
|
|
// If stack grows down, we need to add size of find the lowest
|
|
|
|
// address of the object.
|
|
|
|
Offset += FFI->getObjectSize(i);
|
|
|
|
|
|
|
|
unsigned Align = FFI->getObjectAlignment(i);
|
2009-03-27 06:09:40 +00:00
|
|
|
// If the alignment of this object is greater than that of the stack,
|
|
|
|
// then increase the stack alignment to match.
|
2006-09-28 00:10:27 +00:00
|
|
|
MaxAlign = std::max(MaxAlign, Align);
|
|
|
|
// Adjust to alignment boundary
|
|
|
|
Offset = (Offset+Align-1)/Align*Align;
|
|
|
|
|
|
|
|
FFI->setObjectOffset(i, -Offset); // Set the computed offset
|
|
|
|
}
|
|
|
|
} else {
|
2008-06-03 08:46:59 +00:00
|
|
|
int MaxCSFI = MaxCSFrameIndex, MinCSFI = MinCSFrameIndex;
|
|
|
|
for (int i = MaxCSFI; i >= MinCSFI ; --i) {
|
2006-09-28 00:10:27 +00:00
|
|
|
unsigned Align = FFI->getObjectAlignment(i);
|
2009-03-27 06:09:40 +00:00
|
|
|
// If the alignment of this object is greater than that of the stack,
|
|
|
|
// then increase the stack alignment to match.
|
2006-09-28 00:10:27 +00:00
|
|
|
MaxAlign = std::max(MaxAlign, Align);
|
|
|
|
// Adjust to alignment boundary
|
|
|
|
Offset = (Offset+Align-1)/Align*Align;
|
|
|
|
|
|
|
|
FFI->setObjectOffset(i, Offset);
|
|
|
|
Offset += FFI->getObjectSize(i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-06 10:02:38 +00:00
|
|
|
// Make sure the special register scavenging spill slot is closest to the
|
|
|
|
// frame pointer if a frame pointer is required.
|
2008-02-10 18:45:23 +00:00
|
|
|
const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
|
2009-10-29 02:33:47 +00:00
|
|
|
if (RS && RegInfo->hasFP(Fn) && !RegInfo->needsStackRealignment(Fn)) {
|
2007-03-06 10:02:38 +00:00
|
|
|
int SFI = RS->getScavengingFrameIndex();
|
2008-11-07 01:48:58 +00:00
|
|
|
if (SFI >= 0)
|
|
|
|
AdjustStackOffset(FFI, SFI, StackGrowsDown, Offset, MaxAlign);
|
2007-03-06 10:02:38 +00:00
|
|
|
}
|
|
|
|
|
2008-11-06 02:29:10 +00:00
|
|
|
// Make sure that the stack protector comes before the local variables on the
|
|
|
|
// stack.
|
2008-11-07 01:48:58 +00:00
|
|
|
if (FFI->getStackProtectorIndex() >= 0)
|
|
|
|
AdjustStackOffset(FFI, FFI->getStackProtectorIndex(), StackGrowsDown,
|
|
|
|
Offset, MaxAlign);
|
2008-11-06 02:29:10 +00:00
|
|
|
|
2006-09-28 00:10:27 +00:00
|
|
|
// Then assign frame offsets to stack objects that are not used to spill
|
2007-01-02 21:31:15 +00:00
|
|
|
// callee saved registers.
|
2002-12-28 20:43:30 +00:00
|
|
|
for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
|
2006-09-28 00:10:27 +00:00
|
|
|
if (i >= MinCSFrameIndex && i <= MaxCSFrameIndex)
|
|
|
|
continue;
|
2007-03-06 10:02:38 +00:00
|
|
|
if (RS && (int)i == RS->getScavengingFrameIndex())
|
|
|
|
continue;
|
2008-02-27 03:04:06 +00:00
|
|
|
if (FFI->isDeadObjectIndex(i))
|
|
|
|
continue;
|
2008-11-06 21:37:09 +00:00
|
|
|
if (FFI->getStackProtectorIndex() == (int)i)
|
|
|
|
continue;
|
2006-09-28 00:10:27 +00:00
|
|
|
|
2008-11-07 01:48:58 +00:00
|
|
|
AdjustStackOffset(FFI, i, StackGrowsDown, Offset, MaxAlign);
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
|
|
|
|
2007-03-06 10:02:38 +00:00
|
|
|
// Make sure the special register scavenging spill slot is closest to the
|
|
|
|
// stack pointer.
|
2009-10-29 02:33:47 +00:00
|
|
|
if (RS && (!RegInfo->hasFP(Fn) || RegInfo->needsStackRealignment(Fn))) {
|
2007-03-06 10:02:38 +00:00
|
|
|
int SFI = RS->getScavengingFrameIndex();
|
2008-11-07 01:48:58 +00:00
|
|
|
if (SFI >= 0)
|
|
|
|
AdjustStackOffset(FFI, SFI, StackGrowsDown, Offset, MaxAlign);
|
2007-03-06 10:02:38 +00:00
|
|
|
}
|
|
|
|
|
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
|
|
|
if (!RegInfo->targetHandlesStackFrameRounding()) {
|
2007-05-01 00:52:08 +00:00
|
|
|
// If we have reserved argument space for call sites in the function
|
|
|
|
// immediately on entry to the current function, count it as part of the
|
|
|
|
// overall stack size.
|
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
|
|
|
if (FFI->hasCalls() && RegInfo->hasReservedCallFrame(Fn))
|
2007-01-23 09:38:11 +00:00
|
|
|
Offset += FFI->getMaxCallFrameSize();
|
|
|
|
|
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
|
|
|
// Round up the size to a multiple of the alignment. If the function has
|
|
|
|
// any calls or alloca's, align to the target's StackAlignment value to
|
|
|
|
// ensure that the callee's frame or the alloca data is suitably aligned;
|
|
|
|
// otherwise, for leaf functions, align to the TransientStackAlignment
|
|
|
|
// value.
|
|
|
|
unsigned StackAlign;
|
|
|
|
if (FFI->hasCalls() || FFI->hasVarSizedObjects() ||
|
|
|
|
(RegInfo->needsStackRealignment(Fn) && FFI->getObjectIndexEnd() != 0))
|
|
|
|
StackAlign = TFI.getStackAlignment();
|
|
|
|
else
|
|
|
|
StackAlign = TFI.getTransientStackAlignment();
|
|
|
|
// If the frame pointer is eliminated, all frame offsets will be relative
|
|
|
|
// to SP not FP; align to MaxAlign so this works.
|
|
|
|
StackAlign = std::max(StackAlign, MaxAlign);
|
|
|
|
unsigned AlignMask = StackAlign - 1;
|
2007-04-25 04:30:24 +00:00
|
|
|
Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
|
2007-01-23 09:38:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Update frame info to pretend that this is part of the stack...
|
2009-09-24 16:42:27 +00:00
|
|
|
FFI->setStackSize(Offset - LocalAreaOffset);
|
2005-11-06 17:43:20 +00:00
|
|
|
|
|
|
|
// Remember the required stack alignment in case targets need it to perform
|
|
|
|
// dynamic stack alignment.
|
pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack
alignment is just always 4 bytes. For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.
After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo. This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4. (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
|
|
|
if (MaxAlign > FFI->getMaxAlignment())
|
|
|
|
FFI->setMaxAlignment(MaxAlign);
|
2003-01-15 22:52:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-09-28 00:10:27 +00:00
|
|
|
/// insertPrologEpilogCode - Scan the function for modified callee saved
|
|
|
|
/// registers, insert spill code for these callee saved registers, then add
|
2003-01-15 22:52:34 +00:00
|
|
|
/// prolog and epilog code to the function.
|
|
|
|
///
|
|
|
|
void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
|
2008-04-23 18:19:47 +00:00
|
|
|
const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
|
|
|
|
|
2003-01-15 22:52:34 +00:00
|
|
|
// Add prologue to the function...
|
2008-04-23 18:19:47 +00:00
|
|
|
TRI->emitPrologue(Fn);
|
2003-01-15 22:52:34 +00:00
|
|
|
|
|
|
|
// Add epilogue to restore the callee-save registers in each exiting block
|
|
|
|
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
|
|
|
|
// If last instruction is a return instruction, add an epilogue
|
2008-01-07 07:27:27 +00:00
|
|
|
if (!I->empty() && I->back().getDesc().isReturn())
|
2008-04-23 18:19:47 +00:00
|
|
|
TRI->emitEpilogue(Fn, *I);
|
2003-01-15 22:52:34 +00:00
|
|
|
}
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// replaceFrameIndices - Replace all MO_FrameIndex operands with physical
|
|
|
|
/// register references and actual offsets.
|
|
|
|
///
|
|
|
|
void PEI::replaceFrameIndices(MachineFunction &Fn) {
|
|
|
|
if (!Fn.getFrameInfo()->hasStackObjects()) return; // Nothing to do?
|
|
|
|
|
|
|
|
const TargetMachine &TM = Fn.getTarget();
|
|
|
|
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
|
2008-02-10 18:45:23 +00:00
|
|
|
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
|
2007-05-01 09:01:42 +00:00
|
|
|
const TargetFrameInfo *TFI = TM.getFrameInfo();
|
|
|
|
bool StackGrowsDown =
|
|
|
|
TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
|
2008-02-10 18:45:23 +00:00
|
|
|
int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
|
|
|
|
int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();
|
2002-12-28 20:43:30 +00:00
|
|
|
|
2009-03-27 06:09:40 +00:00
|
|
|
for (MachineFunction::iterator BB = Fn.begin(),
|
|
|
|
E = Fn.end(); BB != E; ++BB) {
|
2007-05-01 09:01:42 +00:00
|
|
|
int SPAdj = 0; // SP offset due to call frame setup / destroy.
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
|
2009-03-27 06:09:40 +00:00
|
|
|
|
2007-04-09 01:19:33 +00:00
|
|
|
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
|
2008-03-03 23:57:28 +00:00
|
|
|
|
|
|
|
if (I->getOpcode() == FrameSetupOpcode ||
|
|
|
|
I->getOpcode() == FrameDestroyOpcode) {
|
|
|
|
// Remember how much SP has been adjusted to create the call
|
|
|
|
// frame.
|
2008-03-20 01:22:40 +00:00
|
|
|
int Size = I->getOperand(0).getImm();
|
2008-03-03 23:57:28 +00:00
|
|
|
|
2008-03-20 01:22:40 +00:00
|
|
|
if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) ||
|
|
|
|
(StackGrowsDown && I->getOpcode() == FrameDestroyOpcode))
|
|
|
|
Size = -Size;
|
2008-03-03 22:11:16 +00:00
|
|
|
|
2008-03-20 01:22:40 +00:00
|
|
|
SPAdj += Size;
|
2008-03-03 23:57:28 +00:00
|
|
|
|
2009-03-19 17:15:43 +00:00
|
|
|
MachineBasicBlock::iterator PrevI = BB->end();
|
|
|
|
if (I != BB->begin()) PrevI = prior(I);
|
2008-03-20 01:22:40 +00:00
|
|
|
TRI.eliminateCallFramePseudoInstr(Fn, *BB, I);
|
2008-03-03 23:57:28 +00:00
|
|
|
|
2008-03-20 01:22:40 +00:00
|
|
|
// Visit the instructions created by eliminateCallFramePseudoInstr().
|
2009-03-19 17:15:43 +00:00
|
|
|
if (PrevI == BB->end())
|
|
|
|
I = BB->begin(); // The replaced instr was the first in the block.
|
|
|
|
else
|
2009-12-03 00:50:42 +00:00
|
|
|
I = llvm::next(PrevI);
|
2008-03-20 01:22:40 +00:00
|
|
|
continue;
|
2007-05-01 09:01:42 +00:00
|
|
|
}
|
2008-03-03 22:11:16 +00:00
|
|
|
|
2009-03-24 20:33:17 +00:00
|
|
|
MachineInstr *MI = I;
|
2008-03-03 23:57:28 +00:00
|
|
|
bool DoIncr = true;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
|
2008-10-03 15:45:36 +00:00
|
|
|
if (MI->getOperand(i).isFI()) {
|
2008-03-20 01:22:40 +00:00
|
|
|
// Some instructions (e.g. inline asm instructions) can have
|
|
|
|
// multiple frame indices and/or cause eliminateFrameIndex
|
|
|
|
// to insert more than one instruction. We need the register
|
|
|
|
// scavenger to go through all of these instructions so that
|
|
|
|
// it can update its register information. We keep the
|
|
|
|
// iterator at the point before insertion so that we can
|
|
|
|
// revisit them in full.
|
|
|
|
bool AtBeginning = (I == BB->begin());
|
|
|
|
if (!AtBeginning) --I;
|
|
|
|
|
|
|
|
// If this instruction has a FrameIndex operand, we need to
|
|
|
|
// use that target machine register info object to eliminate
|
|
|
|
// it.
|
2009-10-07 17:12:56 +00:00
|
|
|
int Value;
|
|
|
|
unsigned VReg =
|
|
|
|
TRI.eliminateFrameIndex(MI, SPAdj, &Value,
|
|
|
|
FrameIndexVirtualScavenging ? NULL : RS);
|
|
|
|
if (VReg) {
|
|
|
|
assert (FrameIndexVirtualScavenging &&
|
|
|
|
"Not scavenging, but virtual returned from "
|
|
|
|
"eliminateFrameIndex()!");
|
|
|
|
FrameConstantRegMap[VReg] = FrameConstantEntry(Value, SPAdj);
|
|
|
|
}
|
2008-03-20 01:22:40 +00:00
|
|
|
|
|
|
|
// Reset the iterator if we were at the beginning of the BB.
|
|
|
|
if (AtBeginning) {
|
|
|
|
I = BB->begin();
|
|
|
|
DoIncr = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
MI = 0;
|
|
|
|
break;
|
|
|
|
}
|
2008-03-03 23:57:28 +00:00
|
|
|
|
2009-03-20 05:08:24 +00:00
|
|
|
if (DoIncr && I != BB->end()) ++I;
|
2008-03-03 23:57:28 +00:00
|
|
|
|
2007-02-23 01:11:26 +00:00
|
|
|
// Update register states.
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
if (RS && !FrameIndexVirtualScavenging && MI) RS->forward(MI);
|
2007-02-23 01:11:26 +00:00
|
|
|
}
|
2008-03-03 22:11:16 +00:00
|
|
|
|
2007-05-01 09:01:42 +00:00
|
|
|
assert(SPAdj == 0 && "Unbalanced call frame setup / destroy pairs?");
|
2007-02-23 01:11:26 +00:00
|
|
|
}
|
2002-12-28 20:43:30 +00:00
|
|
|
}
|
2009-05-11 17:04:19 +00:00
|
|
|
|
2009-10-07 17:12:56 +00:00
|
|
|
/// findLastUseReg - find the killing use of the specified register within
|
|
|
|
/// the instruciton range. Return the operand number of the kill in Operand.
|
|
|
|
static MachineBasicBlock::iterator
|
|
|
|
findLastUseReg(MachineBasicBlock::iterator I, MachineBasicBlock::iterator ME,
|
2009-10-21 15:26:21 +00:00
|
|
|
unsigned Reg) {
|
2009-10-07 17:12:56 +00:00
|
|
|
// Scan forward to find the last use of this virtual register
|
|
|
|
for (++I; I != ME; ++I) {
|
|
|
|
MachineInstr *MI = I;
|
2009-10-21 15:26:21 +00:00
|
|
|
bool isDefInsn = false;
|
|
|
|
bool isKillInsn = false;
|
2009-10-07 17:12:56 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
|
|
|
|
if (MI->getOperand(i).isReg()) {
|
|
|
|
unsigned OpReg = MI->getOperand(i).getReg();
|
|
|
|
if (OpReg == 0 || !TargetRegisterInfo::isVirtualRegister(OpReg))
|
|
|
|
continue;
|
|
|
|
assert (OpReg == Reg
|
|
|
|
&& "overlapping use of scavenged index register!");
|
2009-10-21 15:26:21 +00:00
|
|
|
// If this is the killing use, we have a candidate.
|
|
|
|
if (MI->getOperand(i).isKill())
|
|
|
|
isKillInsn = true;
|
|
|
|
else if (MI->getOperand(i).isDef())
|
|
|
|
isDefInsn = true;
|
2009-10-07 17:12:56 +00:00
|
|
|
}
|
2009-10-21 15:26:21 +00:00
|
|
|
if (isKillInsn && !isDefInsn)
|
|
|
|
return I;
|
2009-10-07 17:12:56 +00:00
|
|
|
}
|
|
|
|
// If we hit the end of the basic block, there was no kill of
|
|
|
|
// the virtual register, which is wrong.
|
|
|
|
assert (0 && "scavenged index register never killed!");
|
|
|
|
return ME;
|
|
|
|
}
|
|
|
|
|
2009-09-29 18:23:15 +00:00
|
|
|
/// scavengeFrameVirtualRegs - Replace all frame index virtual registers
|
|
|
|
/// with physical registers. Use the register scavenger to find an
|
|
|
|
/// appropriate register to use.
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
void PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) {
|
|
|
|
// Run through the instructions and find any virtual registers.
|
|
|
|
for (MachineFunction::iterator BB = Fn.begin(),
|
|
|
|
E = Fn.end(); BB != E; ++BB) {
|
|
|
|
RS->enterBasicBlock(BB);
|
|
|
|
|
2009-10-21 15:26:21 +00:00
|
|
|
// FIXME: The logic flow in this function is still too convoluted.
|
|
|
|
// It needs a cleanup refactoring. Do that in preparation for tracking
|
|
|
|
// more than one scratch register value and using ranges to find
|
|
|
|
// available scratch registers.
|
2009-09-29 18:23:15 +00:00
|
|
|
unsigned CurrentVirtReg = 0;
|
2009-09-30 00:37:40 +00:00
|
|
|
unsigned CurrentScratchReg = 0;
|
2009-10-08 01:09:45 +00:00
|
|
|
bool havePrevValue = false;
|
2009-10-14 21:07:11 +00:00
|
|
|
int PrevValue = 0;
|
2009-10-07 18:44:24 +00:00
|
|
|
MachineInstr *PrevLastUseMI = NULL;
|
|
|
|
unsigned PrevLastUseOp = 0;
|
2009-10-08 01:09:45 +00:00
|
|
|
bool trackingCurrentValue = false;
|
|
|
|
int SPAdj = 0;
|
|
|
|
int Value = 0;
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
|
2009-10-07 17:12:56 +00:00
|
|
|
// The instruction stream may change in the loop, so check BB->end()
|
|
|
|
// directly.
|
2009-10-21 15:26:21 +00:00
|
|
|
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
MachineInstr *MI = I;
|
2009-10-20 19:52:35 +00:00
|
|
|
bool isDefInsn = false;
|
|
|
|
bool isKillInsn = false;
|
2009-10-21 15:26:21 +00:00
|
|
|
bool clobbersScratchReg = false;
|
|
|
|
bool DoIncr = true;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
if (MI->getOperand(i).isReg()) {
|
2009-10-07 17:12:56 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
unsigned Reg = MO.getReg();
|
2009-09-30 20:35:36 +00:00
|
|
|
if (Reg == 0)
|
2009-09-29 18:23:15 +00:00
|
|
|
continue;
|
2009-09-30 20:35:36 +00:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
|
2009-10-07 17:12:56 +00:00
|
|
|
// If we have a previous scratch reg, check and see if anything
|
|
|
|
// here kills whatever value is in there.
|
2009-10-21 15:26:21 +00:00
|
|
|
if (Reg == CurrentScratchReg) {
|
2009-10-07 17:12:56 +00:00
|
|
|
if (MO.isUse()) {
|
|
|
|
// Two-address operands implicitly kill
|
2009-10-21 15:26:21 +00:00
|
|
|
if (MO.isKill() || MI->isRegTiedToDefOperand(i))
|
|
|
|
clobbersScratchReg = true;
|
2009-10-07 17:12:56 +00:00
|
|
|
} else {
|
|
|
|
assert (MO.isDef());
|
2009-10-21 15:26:21 +00:00
|
|
|
clobbersScratchReg = true;
|
2009-10-07 17:12:56 +00:00
|
|
|
}
|
|
|
|
}
|
2009-09-30 20:35:36 +00:00
|
|
|
continue;
|
|
|
|
}
|
2009-10-20 19:52:35 +00:00
|
|
|
// If this is a def, remember that this insn defines the value.
|
|
|
|
// This lets us properly consider insns which re-use the scratch
|
|
|
|
// register, such as r2 = sub r2, #imm, in the middle of the
|
|
|
|
// scratch range.
|
|
|
|
if (MO.isDef())
|
|
|
|
isDefInsn = true;
|
2009-09-29 18:23:15 +00:00
|
|
|
|
2009-10-08 01:09:45 +00:00
|
|
|
// Have we already allocated a scratch register for this virtual?
|
2009-09-29 18:23:15 +00:00
|
|
|
if (Reg != CurrentVirtReg) {
|
2009-10-08 01:09:45 +00:00
|
|
|
// When we first encounter a new virtual register, it
|
|
|
|
// must be a definition.
|
|
|
|
assert(MI->getOperand(i).isDef() &&
|
|
|
|
"frame index virtual missing def!");
|
|
|
|
// We can't have nested virtual register live ranges because
|
|
|
|
// there's only a guarantee of one scavenged register at a time.
|
|
|
|
assert (CurrentVirtReg == 0 &&
|
|
|
|
"overlapping frame index virtual registers!");
|
|
|
|
|
|
|
|
// If the target gave us information about what's in the register,
|
|
|
|
// we can use that to re-use scratch regs.
|
|
|
|
DenseMap<unsigned, FrameConstantEntry>::iterator Entry =
|
|
|
|
FrameConstantRegMap.find(Reg);
|
|
|
|
trackingCurrentValue = Entry != FrameConstantRegMap.end();
|
|
|
|
if (trackingCurrentValue) {
|
|
|
|
SPAdj = (*Entry).second.second;
|
|
|
|
Value = (*Entry).second.first;
|
|
|
|
} else
|
|
|
|
SPAdj = Value = 0;
|
2009-10-07 17:12:56 +00:00
|
|
|
|
|
|
|
// If the scratch register from the last allocation is still
|
|
|
|
// available, see if the value matches. If it does, just re-use it.
|
2009-10-08 01:09:45 +00:00
|
|
|
if (trackingCurrentValue && havePrevValue && PrevValue == Value) {
|
2009-10-07 17:12:56 +00:00
|
|
|
// FIXME: This assumes that the instructions in the live range
|
|
|
|
// for the virtual register are exclusively for the purpose
|
2009-10-07 19:08:36 +00:00
|
|
|
// of populating the value in the register. That's reasonable
|
2009-10-07 17:12:56 +00:00
|
|
|
// for these frame index registers, but it's still a very, very
|
2009-10-21 15:26:21 +00:00
|
|
|
// strong assumption. rdar://7322732. Better would be to
|
|
|
|
// explicitly check each instruction in the range for references
|
|
|
|
// to the virtual register. Only delete those insns that
|
|
|
|
// touch the virtual register.
|
2009-10-07 17:12:56 +00:00
|
|
|
|
|
|
|
// Find the last use of the new virtual register. Remove all
|
|
|
|
// instruction between here and there, and update the current
|
|
|
|
// instruction to reference the last use insn instead.
|
|
|
|
MachineBasicBlock::iterator LastUseMI =
|
2009-10-21 15:26:21 +00:00
|
|
|
findLastUseReg(I, BB->end(), Reg);
|
|
|
|
|
2009-10-07 17:12:56 +00:00
|
|
|
// Remove all instructions up 'til the last use, since they're
|
|
|
|
// just calculating the value we already have.
|
|
|
|
BB->erase(I, LastUseMI);
|
|
|
|
MI = I = LastUseMI;
|
|
|
|
|
2009-10-21 15:26:21 +00:00
|
|
|
// Extend the live range of the scratch register
|
2009-10-07 17:12:56 +00:00
|
|
|
PrevLastUseMI->getOperand(PrevLastUseOp).setIsKill(false);
|
|
|
|
RS->setUsed(CurrentScratchReg);
|
|
|
|
CurrentVirtReg = Reg;
|
|
|
|
|
2009-10-21 15:26:21 +00:00
|
|
|
// We deleted the instruction we were scanning the operands of.
|
|
|
|
// Jump back to the instruction iterator loop. Don't increment
|
|
|
|
// past this instruction since we updated the iterator already.
|
|
|
|
DoIncr = false;
|
|
|
|
break;
|
2009-10-07 17:12:56 +00:00
|
|
|
}
|
2009-10-21 15:26:21 +00:00
|
|
|
|
|
|
|
// Scavenge a new scratch register
|
|
|
|
CurrentVirtReg = Reg;
|
|
|
|
const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
|
|
|
|
CurrentScratchReg = RS->FindUnusedReg(RC);
|
|
|
|
if (CurrentScratchReg == 0)
|
|
|
|
// No register is "free". Scavenge a register.
|
|
|
|
CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
|
|
|
|
|
|
|
|
PrevValue = Value;
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
}
|
2009-10-21 15:26:21 +00:00
|
|
|
// replace this reference to the virtual register with the
|
|
|
|
// scratch register.
|
2009-09-29 18:23:15 +00:00
|
|
|
assert (CurrentScratchReg && "Missing scratch register!");
|
|
|
|
MI->getOperand(i).setReg(CurrentScratchReg);
|
|
|
|
|
2009-10-07 17:12:56 +00:00
|
|
|
if (MI->getOperand(i).isKill()) {
|
2009-10-20 19:52:35 +00:00
|
|
|
isKillInsn = true;
|
2009-10-07 18:44:24 +00:00
|
|
|
PrevLastUseOp = i;
|
2009-10-20 19:52:35 +00:00
|
|
|
PrevLastUseMI = MI;
|
2009-10-07 17:12:56 +00:00
|
|
|
}
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
}
|
2009-10-21 15:26:21 +00:00
|
|
|
}
|
2009-10-20 19:52:35 +00:00
|
|
|
// If this is the last use of the scratch, stop tracking it. The
|
|
|
|
// last use will be a kill operand in an instruction that does
|
|
|
|
// not also define the scratch register.
|
|
|
|
if (isKillInsn && !isDefInsn) {
|
2009-10-21 15:26:21 +00:00
|
|
|
CurrentVirtReg = 0;
|
2009-10-20 19:52:35 +00:00
|
|
|
havePrevValue = trackingCurrentValue;
|
|
|
|
}
|
2009-10-21 15:26:21 +00:00
|
|
|
// Similarly, notice if instruction clobbered the value in the
|
|
|
|
// register we're tracking for possible later reuse. This is noted
|
|
|
|
// above, but enforced here since the value is still live while we
|
|
|
|
// process the rest of the operands of the instruction.
|
|
|
|
if (clobbersScratchReg) {
|
|
|
|
havePrevValue = false;
|
|
|
|
CurrentScratchReg = 0;
|
|
|
|
}
|
|
|
|
if (DoIncr) {
|
|
|
|
RS->forward(I);
|
|
|
|
++I;
|
|
|
|
}
|
Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.
Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.
For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 23:52:18 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|