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llvm-6502/test/CodeGen/X86/atomic-or.ll

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Fix a small thinko for constant i64 lock/orq optimization where we we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 00:48:30 +00:00
; RUN: llc < %s -march=x86-64 | FileCheck %s
; rdar://9692967
TargetConstant immediates won't be placed into registers so tighten up the valid constant check earlier. rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 23:04:38 +00:00
define void @t1(i64* %p, i32 %b) nounwind {
Fix a small thinko for constant i64 lock/orq optimization where we we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 00:48:30 +00:00
entry:
%p.addr = alloca i64*, align 8
store i64* %p, i64** %p.addr, align 8
%tmp = load i64** %p.addr, align 8
TargetConstant immediates won't be placed into registers so tighten up the valid constant check earlier. rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 23:04:38 +00:00
; CHECK: t1:
; CHECK: movl $2147483648, %eax
Fix a small thinko for constant i64 lock/orq optimization where we we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 00:48:30 +00:00
; CHECK: lock
Be less specific about register allocation ordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 04:06:41 +00:00
; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
Convert a bunch more tests over to the new atomic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:15:09 +00:00
%0 = atomicrmw or i64* %tmp, i64 2147483648 seq_cst
Fix a small thinko for constant i64 lock/orq optimization where we we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 00:48:30 +00:00
ret void
}
TargetConstant immediates won't be placed into registers so tighten up the valid constant check earlier. rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 23:04:38 +00:00
define void @t2(i64* %p, i32 %b) nounwind {
entry:
%p.addr = alloca i64*, align 8
store i64* %p, i64** %p.addr, align 8
%tmp = load i64** %p.addr, align 8
; CHECK: t2:
; CHECK: lock
Be less specific about register allocation ordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134308 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 04:06:41 +00:00
; CHECK-NEXT: orq $2147483644, (%r{{.*}})
Convert a bunch more tests over to the new atomic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 23:15:09 +00:00
%0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
TargetConstant immediates won't be placed into registers so tighten up the valid constant check earlier. rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 23:04:38 +00:00
ret void
}
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