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https://github.com/c64scene-ar/llvm-6502.git
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34 lines
926 B
LLVM
34 lines
926 B
LLVM
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that gp-relative instructions are being generated.
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@a = common global i32 0, align 4
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@b = common global i32 0, align 4
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@c = common global i32 0, align 4
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define i32 @foo(i32 %p) #0 {
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entry:
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#a)
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#b)
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; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}}
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%0 = load i32* @a, align 4
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%1 = load i32* @b, align 4
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%add = add nsw i32 %1, %0
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%cmp = icmp eq i32 %0, %1
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br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
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entry.if.end_crit_edge:
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%.pre = load i32* @c, align 4
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br label %if.end
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if.then:
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%add1 = add nsw i32 %add, %0
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store i32 %add1, i32* @c, align 4
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br label %if.end
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if.end:
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%2 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %add1, %if.then ]
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%cmp2 = icmp eq i32 %add, %2
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%sel1 = select i1 %cmp2, i32 %2, i32 %1
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ret i32 %sel1
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}
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