llvm-6502/test/CodeGen/PowerPC/ppcf128-2.ll

; RUN: llc < %s -march=ppc64

define i64 @__fixtfdi(ppc_fp128 %a) nounwind  {
entry:
        br i1 false, label %bb, label %bb8
bb:             ; preds = %entry
        %tmp5 = fsub ppc_fp128 0xM80000000000000000000000000000000, %a           ; <ppc_fp128> [#uses=1]
        %tmp6 = tail call i64 @__fixunstfdi( ppc_fp128 %tmp5 ) nounwind                 ; <i64> [#uses=0]
        ret i64 0
bb8:            ; preds = %entry
        ret i64 0
}

declare i64 @__fixunstfdi(ppc_fp128)
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-09 00:09:15 +00:00			`; RUN: llc < %s -march=ppc64`
More APInt-ification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48344 91177308-0d34-0410-b5e6-96231b3b80d8 2008-03-13 22:13:53 +00:00
			`define i64 @__fixtfdi(ppc_fp128 %a) nounwind {`
			`entry:`
			`br i1 false, label %bb, label %bb8`
			`bb: ; preds = %entry`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-04 22:49:04 +00:00			`%tmp5 = fsub ppc_fp128 0xM80000000000000000000000000000000, %a ; <ppc_fp128> [#uses=1]`
More APInt-ification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48344 91177308-0d34-0410-b5e6-96231b3b80d8 2008-03-13 22:13:53 +00:00			`%tmp6 = tail call i64 @__fixunstfdi( ppc_fp128 %tmp5 ) nounwind ; <i64> [#uses=0]`
			`ret i64 0`
			`bb8: ; preds = %entry`
			`ret i64 0`
			`}`

			`declare i64 @__fixunstfdi(ppc_fp128)`