llvm-6502/test/CodeGen/X86/rem-2.ll

; RUN: llc < %s -march=x86 | not grep cltd

define i32 @test(i32 %X) nounwind readnone {
entry:
	%0 = srem i32 41, %X
	ret i32 %0
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-08 23:54:48 +00:00			`; RUN: llc < %s -march=x86 \| not grep cltd`
DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8 2009-01-19 19:06:11 +00:00
			`define i32 @test(i32 %X) nounwind readnone {`
			`entry:`
			`%0 = srem i32 41, %X`
			`ret i32 %0`
			`}`