2014-10-20 16:08:33 +00:00
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; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
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[AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.
Examples:
1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
to b.<invCC>
2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
to b.<CC>
rdar://problem/18506500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219742 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-14 23:07:53 +00:00
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; Checks for conditional branch b.vs
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; Function Attrs: nounwind
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define i32 @add(i32, i32) {
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entry:
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%2 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1)
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%3 = extractvalue { i32, i1 } %2, 1
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br i1 %3, label %6, label %4
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; <label>:4 ; preds = %entry
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%5 = extractvalue { i32, i1 } %2, 0
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ret i32 %5
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; <label>:6 ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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; CHECK: b.vs
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}
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2014-10-20 16:08:33 +00:00
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%S64 = type <{ i64 }>
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%S32 = type <{ i32 }>
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%Sstruct = type <{ %S64, %S32 }>
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; Checks for compfail when optimizing csincr-cbz sequence
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define { i64, i1 } @foo(i64* , %Sstruct* , i1, i64) {
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entry:
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%.sroa.0 = alloca i72, align 16
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%.count.value = getelementptr inbounds %Sstruct* %1, i64 0, i32 0, i32 0
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%4 = load i64* %.count.value, align 8
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%.repeatedValue.value = getelementptr inbounds %Sstruct* %1, i64 0, i32 1, i32 0
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%5 = load i32* %.repeatedValue.value, align 8
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%6 = icmp eq i64 %4, 0
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br label %7
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; <label>:7 ; preds = %entry
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%.mask58 = and i32 %5, -2048
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%8 = icmp eq i32 %.mask58, 55296
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%.not134 = xor i1 %8, true
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%9 = icmp eq i32 %5, 1114112
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%or.cond135 = and i1 %9, %.not134
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br i1 %or.cond135, label %10, label %.loopexit
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; <label>:10 ; preds = %7
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%11 = and i32 %5, -2048
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%12 = icmp eq i32 %11, 55296
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br i1 %12, label %.loopexit, label %10
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.loopexit: ; preds = %.entry,%7,%10
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tail call void @llvm.trap()
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unreachable
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}
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[AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.
Examples:
1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
to b.<invCC>
2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
to b.<CC>
rdar://problem/18506500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219742 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-14 23:07:53 +00:00
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; Function Attrs: nounwind readnone
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declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
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; Function Attrs: noreturn nounwind
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declare void @llvm.trap()
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