6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity
60d8767211
llvm-6502/test/MC/X86/intel-syntax-encoding.s

79 lines
1.7 KiB
ArmAsm
Raw Normal View History

Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 17:53:25 +00:00
// RUN: llvm-mc -x86-asm-syntax=intel -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encoding: [0x66,0x83,0xf0,0x0c]
xor ax, 12
// CHECK: encoding: [0x83,0xf0,0x0c]
xor eax, 12
// CHECK: encoding: [0x48,0x83,0xf0,0x0c]
xor rax, 12
// CHECK: encoding: [0x66,0x83,0xc8,0x0c]
or ax, 12
// CHECK: encoding: [0x83,0xc8,0x0c]
or eax, 12
// CHECK: encoding: [0x48,0x83,0xc8,0x0c]
or rax, 12
// CHECK: encoding: [0x66,0x83,0xf8,0x0c]
cmp ax, 12
// CHECK: encoding: [0x83,0xf8,0x0c]
cmp eax, 12
// CHECK: encoding: [0x48,0x83,0xf8,0x0c]
cmp rax, 12
Intel syntax: There is no need to create unary expr for simple negative displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:15:51 +00:00
// CHECK: encoding: [0x48,0x89,0x44,0x24,0xf0]
mov QWORD PTR [RSP - 16], RAX
Post process 'and', 'sub' instructions and select better encoding, if available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:40:55 +00:00
// CHECK: encoding: [0x66,0x83,0xc0,0xf4]
add ax, -12
// CHECK: encoding: [0x83,0xc0,0xf4]
add eax, -12
// CHECK: encoding: [0x48,0x83,0xc0,0xf4]
add rax, -12
Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 03:34:55 +00:00
// CHECK: encoding: [0x66,0x83,0xd0,0xf4]
adc ax, -12
// CHECK: encoding: [0x83,0xd0,0xf4]
adc eax, -12
// CHECK: encoding: [0x48,0x83,0xd0,0xf4]
adc rax, -12
// CHECK: encoding: [0x66,0x83,0xd8,0xf4]
sbb ax, -12
// CHECK: encoding: [0x83,0xd8,0xf4]
sbb eax, -12
// CHECK: encoding: [0x48,0x83,0xd8,0xf4]
sbb rax, -12
Refactor some duplicated code into helper functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 02:53:34 +00:00
// CHECK: encoding: [0x66,0x83,0xf8,0xf4]
cmp ax, -12
// CHECK: encoding: [0x83,0xf8,0xf4]
cmp eax, -12
// CHECK: encoding: [0x48,0x83,0xf8,0xf4]
cmp rax, -12
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:14:06 +00:00
LBB0_3:
// CHECK: encoding: [0xeb,A]
jmp LBB0_3
Intel syntax: Parse ... PTR [-8] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:21:01 +00:00
// CHECK: encoding: [0xf2,0x0f,0x10,0x2c,0x25,0xf8,0xff,0xff,0xff]
movsd XMM5, QWORD PTR [-8]
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:43:36 +00:00
// CHECK: encoding: [0xd1,0xe7]
shl EDI, 1
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 22:47:12 +00:00
// CHECK: encoding: [0x0f,0xc2,0xd1,0x01]
cmpltps XMM2, XMM1
Add retw and lretw instructions. Also, fix Intel syntax parsing for all ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 01:10:53 +00:00
// CHECK: encoding: [0xc3]
ret
// CHECK: encoding: [0xcb]
retf
// CHECK: encoding: [0xc2,0x08,0x00]
ret 8
// CHECK: encoding: [0xca,0x08,0x00]
retf 8
Reference in New Issue Copy Permalink