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llvm-6502/test/MC/X86/x86_64-encoding.s

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Fixed the encoding problems of the crc32 instructions. All had the Operand size override prefix and only the r/m16 forms should have had that. Also for variant one, the AT&T syntax, added suffixes to all forms. Also added the missing 64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and tweaked one test case to add the needed suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 20:04:42 +00:00
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
Implement the major chunk of PR7195: support for 'callw' in the integrated assembler. Still some discussion to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
// PR7195
// CHECK: callw 42
// CHECK: encoding: [0x66,0xe8,A,A]
callw 42
Move AVX encoding tests to different files git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 21:25:26 +00:00
Rework segment prefix emission code to handle segments in memory operands at the same type as hard coded segments. This fixes problems where we'd emit the segment override after the REX prefix on instructions like: mov %gs:(%rdi), %rax This fixes rdar://8127102. I have several cleanup patches coming next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:28:12 +00:00
// rdar://8127102
// CHECK: movq %gs:(%rdi), %rax
// CHECK: encoding: [0x65,0x48,0x8b,0x07]
movq %gs:(%rdi), %rax
Implement the major chunk of PR7195: support for 'callw' in the integrated assembler. Still some discussion to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
Fixed the encoding problems of the crc32 instructions. All had the Operand size override prefix and only the r/m16 forms should have had that. Also for variant one, the AT&T syntax, added suffixes to all forms. Also added the missing 64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and tweaked one test case to add the needed suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 20:04:42 +00:00
// CHECK: crc32b %bl, %eax
// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0xc3]
crc32b %bl, %eax
// CHECK: crc32b 4(%rbx), %eax
// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0x43,0x04]
crc32b 4(%rbx), %eax
// CHECK: crc32w %bx, %eax
// CHECK: encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc3]
crc32w %bx, %eax
// CHECK: crc32w 4(%rbx), %eax
// CHECK: encoding: [0x66,0xf2,0x0f,0x38,0xf1,0x43,0x04]
crc32w 4(%rbx), %eax
// CHECK: crc32l %ebx, %eax
// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0xc3]
crc32l %ebx, %eax
// CHECK: crc32l 4(%rbx), %eax
// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x43,0x04]
crc32l 4(%rbx), %eax
// CHECK: crc32l 3735928559(%rbx,%rcx,8), %ecx
// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x8c,0xcb,0xef,0xbe,0xad,0xde]
crc32l 0xdeadbeef(%rbx,%rcx,8),%ecx
// CHECK: crc32l 69, %ecx
// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0c,0x25,0x45,0x00,0x00,0x00]
crc32l 0x45,%ecx
// CHECK: crc32l 32493, %ecx
// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xed,0x7e,0x00,0x00]
crc32l 0x7eed,%ecx
// CHECK: crc32l 3133065982, %ecx
// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xfe,0xca,0xbe,0xba]
crc32l 0xbabecafe,%ecx
// CHECK: crc32l %ecx, %ecx
// CHECK: encoding: [0xf2,0x0f,0x38,0xf1,0xc9]
crc32l %ecx,%ecx
// CHECK: crc32b %r11b, %eax
// CHECK: encoding: [0xf2,0x41,0x0f,0x38,0xf0,0xc3]
crc32b %r11b, %eax
// CHECK: crc32b 4(%rbx), %eax
// CHECK: encoding: [0xf2,0x0f,0x38,0xf0,0x43,0x04]
crc32b 4(%rbx), %eax
// CHECK: crc32b %dil, %rax
// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf0,0xc7]
crc32b %dil,%rax
// CHECK: crc32b %r11b, %rax
// CHECK: encoding: [0xf2,0x49,0x0f,0x38,0xf0,0xc3]
crc32b %r11b,%rax
// CHECK: crc32b 4(%rbx), %rax
// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf0,0x43,0x04]
crc32b 4(%rbx), %rax
// CHECK: crc32q %rbx, %rax
// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf1,0xc3]
crc32q %rbx, %rax
// CHECK: crc32q 4(%rbx), %rax
// CHECK: encoding: [0xf2,0x48,0x0f,0x38,0xf1,0x43,0x04]
crc32q 4(%rbx), %rax
Fix an mmx movd encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:51:08 +00:00
// CHECK: movd %r8, %mm1
// CHECK: encoding: [0x49,0x0f,0x6e,0xc8]
movd %r8, %mm1
// CHECK: movd %r8d, %mm1
// CHECK: encoding: [0x41,0x0f,0x6e,0xc8]
movd %r8d, %mm1
// CHECK: movd %rdx, %mm1
// CHECK: encoding: [0x48,0x0f,0x6e,0xca]
movd %rdx, %mm1
// CHECK: movd %edx, %mm1
// CHECK: encoding: [0x0f,0x6e,0xca]
movd %edx, %mm1
// CHECK: movd %mm1, %r8
// CHECK: encoding: [0x49,0x0f,0x7e,0xc8]
movd %mm1, %r8
// CHECK: movd %mm1, %r8d
// CHECK: encoding: [0x41,0x0f,0x7e,0xc8]
movd %mm1, %r8d
// CHECK: movd %mm1, %rdx
// CHECK: encoding: [0x48,0x0f,0x7e,0xca]
movd %mm1, %rdx
// CHECK: movd %mm1, %edx
// CHECK: encoding: [0x0f,0x7e,0xca]
movd %mm1, %edx
Reapply r105521, this time appending "LLU" to 64 bit immediates to avoid breaking the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:51:23 +00:00
Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion during test runs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22 21:11:51 +00:00
// rdar://7840289
// CHECK: pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A]
// CHECK: fixup A - offset: 5, value: CPI1_0-4
pshufb CPI1_0(%rip), %xmm1
Partial support for Intel SHA Extensions (sha1rnds4) Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12 15:51:31 +00:00
// CHECK: sha1rnds4 $1, %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x3a,0xcc,0xd1,0x01]
sha1rnds4 $1, %xmm1, %xmm2
// CHECK: sha1rnds4 $1, (%rax), %xmm2
// CHECK: encoding: [0x0f,0x3a,0xcc,0x10,0x01]
sha1rnds4 $1, (%rax), %xmm2
Add the remaining Intel SHA instructions Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-14 15:03:21 +00:00
// CHECK: sha1nexte %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x38,0xc8,0xd1]
sha1nexte %xmm1, %xmm2
// CHECK: sha1msg1 %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x38,0xc9,0xd1]
sha1msg1 %xmm1, %xmm2
// CHECK: sha1msg1 (%rax), %xmm2
// CHECK: encoding: [0x0f,0x38,0xc9,0x10]
sha1msg1 (%rax), %xmm2
// CHECK: sha1msg2 %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x38,0xca,0xd1]
sha1msg2 %xmm1, %xmm2
// CHECK: sha1msg2 (%rax), %xmm2
// CHECK: encoding: [0x0f,0x38,0xca,0x10]
sha1msg2 (%rax), %xmm2
// CHECK: sha256rnds2 (%rax), %xmm2
// CHECK: encoding: [0x0f,0x38,0xcb,0x10]
sha256rnds2 (%rax), %xmm2
// CHECK: sha256rnds2 %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x38,0xcb,0xd1]
sha256rnds2 %xmm1, %xmm2
// CHECK: sha256rnds2 (%rax), %xmm2
// CHECK: encoding: [0x0f,0x38,0xcb,0x10]
sha256rnds2 %xmm0, (%rax), %xmm2
// CHECK: sha256rnds2 %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x38,0xcb,0xd1]
sha256rnds2 %xmm0, %xmm1, %xmm2
// CHECK: sha256msg1 %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x38,0xcc,0xd1]
sha256msg1 %xmm1, %xmm2
// CHECK: sha256msg1 (%rax), %xmm2
// CHECK: encoding: [0x0f,0x38,0xcc,0x10]
sha256msg1 (%rax), %xmm2
// CHECK: sha256msg2 %xmm1, %xmm2
// CHECK: encoding: [0x0f,0x38,0xcd,0xd1]
sha256msg2 %xmm1, %xmm2
// CHECK: sha256msg2 (%rax), %xmm2
// CHECK: encoding: [0x0f,0x38,0xcd,0x10]
sha256msg2 (%rax), %xmm2
Support x86 "eiz" and "riz" pseudo index registers in the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 00:06:39 +00:00
// CHECK: movq 57005(,%riz), %rbx
// CHECK: encoding: [0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00]
movq 57005(,%riz), %rbx
// CHECK: movq 48879(,%riz), %rax
// CHECK: encoding: [0x48,0x8b,0x04,0x25,0xef,0xbe,0x00,0x00]
movq 48879(,%riz), %rax
// CHECK: movq -4(,%riz,8), %rax
// CHECK: encoding: [0x48,0x8b,0x04,0xe5,0xfc,0xff,0xff,0xff]
movq -4(,%riz,8), %rax
// CHECK: movq (%rcx,%riz), %rax
// CHECK: encoding: [0x48,0x8b,0x04,0x21]
movq (%rcx,%riz), %rax
// CHECK: movq (%rcx,%riz,8), %rax
// CHECK: encoding: [0x48,0x8b,0x04,0xe1]
movq (%rcx,%riz,8), %rax
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64. These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use 64-bit pointer values instead of 32-bit pointer values in the memory map they dump and restore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-12 23:24:13 +00:00
// CHECK: fxsaveq (%rax)
// CHECK: encoding: [0x48,0x0f,0xae,0x00]
fxsaveq (%rax)
// CHECK: fxrstorq (%rax)
// CHECK: encoding: [0x48,0x0f,0xae,0x08]
fxrstorq (%rax)
Recognize leavel and leaveq aliases for leave. Validate encoding of leave in 64bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17 23:36:39 +00:00
// CHECK: leave
// CHECK: encoding: [0xc9]
leave
// CHECK: leave
// CHECK: encoding: [0xc9]
leaveq
Add encoding tests for flds/filds git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 19:25:31 +00:00
// CHECK: flds (%edi)
// CHECK: encoding: [0x67,0xd9,0x07]
flds (%edi)
// CHECK: filds (%edi)
// CHECK: encoding: [0x67,0xdf,0x07]
filds (%edi)
// CHECK: flds (%rdi)
// CHECK: encoding: [0xd9,0x07]
flds (%rdi)
// CHECK: filds (%rdi)
// CHECK: encoding: [0xdf,0x07]
filds (%rdi)
Allow non-AVX form of pmovmskb to take a GR64 operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 05:33:31 +00:00
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 04:55:01 +00:00
// CHECK: pmovmskb %xmm5, %ecx
Allow non-AVX form of pmovmskb to take a GR64 operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 05:33:31 +00:00
// CHECK: encoding: [0x66,0x0f,0xd7,0xcd]
pmovmskb %xmm5,%rcx
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 01:21:22 +00:00
// CHECK: pinsrw $3, %ecx, %xmm5
// CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]
pinsrw $3, %ecx, %xmm5
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 04:55:01 +00:00
// CHECK: pinsrw $3, %ecx, %xmm5
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-14 01:21:22 +00:00
// CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]
pinsrw $3, %rcx, %xmm5
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