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llvm-6502/test/CodeGen/X86/chain_order.ll

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X86: Fix a bug in EltsFromConsecutiveLoads. We can't generate new loads without chains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 19:28:41 +00:00
; RUN: llc < %s -mcpu=corei7-avx -mtriple=x86_64-linux | FileCheck %s
Update to more CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change. All changes were made by the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" grep -q "^; *RUN: *llc.*debug" $NAME && continue grep -q "^; *RUN:.*llvm-objdump" $NAME && continue grep -q "^; *RUN: *opt.*" $NAME && continue TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\([A-Za-z0-9_-]*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC[:]* *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME done This script catches a superset of the cases caught by the script associated with commit r186280. It initially found some false positives due to unusual constructs in a minority of tests; all such cases were disambiguated first in commit r186621. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-18 22:47:09 +00:00
;CHECK-LABEL: cftx020:
X86: Fix a bug in EltsFromConsecutiveLoads. We can't generate new loads without chains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 19:28:41 +00:00
;CHECK: vmovsd (%rdi), %xmm{{.*}}
;CHECK: vmovsd 16(%rdi), %xmm{{.*}}
Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:48:58 +00:00
;CHECK: vmovsd 24(%rdi), %xmm{{.*}}
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 23:33:07 +00:00
;CHECK: vmovhpd 8(%rdi), %xmm{{.*}}
X86: Fix a bug in EltsFromConsecutiveLoads. We can't generate new loads without chains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22 19:28:41 +00:00
;CHECK: vmovupd %xmm{{.*}}, (%rdi)
;CHECK: vmovupd %xmm{{.*}}, 16(%rdi)
;CHECK: ret
; A test from pifft (after SLP-vectorization) that fails when we drop the chain on newly merged loads.
define void @cftx020(double* nocapture %a) {
entry:
%0 = load double* %a, align 8
%arrayidx1 = getelementptr inbounds double* %a, i64 2
%1 = load double* %arrayidx1, align 8
%arrayidx2 = getelementptr inbounds double* %a, i64 1
%2 = load double* %arrayidx2, align 8
%arrayidx3 = getelementptr inbounds double* %a, i64 3
%3 = load double* %arrayidx3, align 8
%4 = insertelement <2 x double> undef, double %0, i32 0
%5 = insertelement <2 x double> %4, double %3, i32 1
%6 = insertelement <2 x double> undef, double %1, i32 0
%7 = insertelement <2 x double> %6, double %2, i32 1
%8 = fadd <2 x double> %5, %7
%9 = bitcast double* %a to <2 x double>*
store <2 x double> %8, <2 x double>* %9, align 8
%10 = insertelement <2 x double> undef, double %0, i32 0
%11 = insertelement <2 x double> %10, double %2, i32 1
%12 = insertelement <2 x double> undef, double %1, i32 0
%13 = insertelement <2 x double> %12, double %3, i32 1
%14 = fsub <2 x double> %11, %13
%15 = bitcast double* %arrayidx1 to <2 x double>*
store <2 x double> %14, <2 x double>* %15, align 8
ret void
}
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