2012-09-20 21:35:21 +00:00
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; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s
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2011-03-30 23:01:21 +00:00
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define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bsli8:
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2011-11-14 23:03:21 +00:00
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;CHECK: vldr
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;CHECK: vldr
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = load <8 x i8>, <8 x i8>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <8 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%tmp6 = and <8 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
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%tmp7 = or <8 x i8> %tmp4, %tmp6
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ret <8 x i8> %tmp7
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}
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define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bsli16:
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2011-11-14 23:03:21 +00:00
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;CHECK: vldr
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;CHECK: vldr
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = load <4 x i16>, <4 x i16>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <4 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3>
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%tmp6 = and <4 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4>
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%tmp7 = or <4 x i16> %tmp4, %tmp6
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ret <4 x i16> %tmp7
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}
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define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bsli32:
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2011-11-14 23:03:21 +00:00
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;CHECK: vldr
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;CHECK: vldr
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = load <2 x i32>, <2 x i32>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <2 x i32> %tmp1, <i32 3, i32 3>
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%tmp6 = and <2 x i32> %tmp3, <i32 -4, i32 -4>
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%tmp7 = or <2 x i32> %tmp4, %tmp6
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ret <2 x i32> %tmp7
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}
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define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bsli64:
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2011-11-14 23:03:21 +00:00
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;CHECK: vldr
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;CHECK: vldr
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;CHECK: vldr
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <1 x i64>, <1 x i64>* %A
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%tmp2 = load <1 x i64>, <1 x i64>* %B
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%tmp3 = load <1 x i64>, <1 x i64>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <1 x i64> %tmp1, <i64 3>
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%tmp6 = and <1 x i64> %tmp3, <i64 -4>
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%tmp7 = or <1 x i64> %tmp4, %tmp6
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ret <1 x i64> %tmp7
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}
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define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bslQi8:
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2012-09-18 01:42:45 +00:00
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;CHECK: vld1.32
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;CHECK: vld1.32
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = load <16 x i8>, <16 x i8>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <16 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>
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%tmp7 = or <16 x i8> %tmp4, %tmp6
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ret <16 x i8> %tmp7
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}
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define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bslQi16:
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2012-09-18 01:42:45 +00:00
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;CHECK: vld1.32
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;CHECK: vld1.32
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = load <8 x i16>, <8 x i16>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <8 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
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%tmp6 = and <8 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4>
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%tmp7 = or <8 x i16> %tmp4, %tmp6
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ret <8 x i16> %tmp7
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}
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define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bslQi32:
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2012-09-18 01:42:45 +00:00
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;CHECK: vld1.32
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;CHECK: vld1.32
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = load <4 x i32>, <4 x i32>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <4 x i32> %tmp1, <i32 3, i32 3, i32 3, i32 3>
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%tmp6 = and <4 x i32> %tmp3, <i32 -4, i32 -4, i32 -4, i32 -4>
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%tmp7 = or <4 x i32> %tmp4, %tmp6
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ret <4 x i32> %tmp7
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}
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define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
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2013-07-14 06:24:09 +00:00
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;CHECK-LABEL: v_bslQi64:
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2012-09-18 01:42:45 +00:00
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;CHECK: vld1.32
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;CHECK: vld1.32
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;CHECK: vld1.64
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2011-03-30 23:01:21 +00:00
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;CHECK: vbsl
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2015-02-27 21:17:42 +00:00
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = load <2 x i64>, <2 x i64>* %B
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%tmp3 = load <2 x i64>, <2 x i64>* %C
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2011-03-30 23:01:21 +00:00
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%tmp4 = and <2 x i64> %tmp1, <i64 3, i64 3>
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%tmp6 = and <2 x i64> %tmp3, <i64 -4, i64 -4>
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%tmp7 = or <2 x i64> %tmp4, %tmp6
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ret <2 x i64> %tmp7
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}
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