2010-12-08 20:04:29 +00:00
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//=- llvm/CodeGen/ScoreboardHazardRecognizer.h - Schedule Support -*- C++ -*-=//
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2010-06-14 21:06:53 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2010-12-08 20:04:29 +00:00
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// This file defines the ScoreboardHazardRecognizer class, which
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// encapsulates hazard-avoidance heuristics for scheduling, based on the
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2010-06-14 21:06:53 +00:00
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// scheduling itineraries specified for the target.
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//
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//===----------------------------------------------------------------------===//
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2010-12-08 20:04:29 +00:00
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#ifndef LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
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#define LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
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2010-06-14 21:06:53 +00:00
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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2010-11-29 18:16:10 +00:00
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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2010-06-14 22:44:26 +00:00
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#include <cstring>
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2010-06-14 21:06:53 +00:00
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namespace llvm {
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class InstrItineraryData;
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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class ScheduleDAG;
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class SUnit;
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class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer {
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// Scoreboard to track function unit usage. Scoreboard[0] is a
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2010-06-14 21:06:53 +00:00
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// mask of the FUs in use in the cycle currently being
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2010-12-08 20:04:29 +00:00
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// schedule. Scoreboard[1] is a mask for the next cycle. The
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// Scoreboard is used as a circular buffer with the current cycle
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2010-06-14 21:06:53 +00:00
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// indicated by Head.
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2010-12-08 20:04:29 +00:00
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//
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// Scoreboard always counts cycles in forward execution order. If used by a
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// bottom-up scheduler, then the scoreboard cycles are the inverse of the
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// scheduler's cycles.
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class Scoreboard {
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unsigned *Data;
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// The maximum number of cycles monitored by the Scoreboard. This
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// value is determined based on the target itineraries to ensure
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// that all hazards can be tracked.
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size_t Depth;
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// Indices into the Scoreboard that represent the current cycle.
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size_t Head;
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public:
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Scoreboard():Data(NULL), Depth(0), Head(0) { }
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~Scoreboard() {
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delete[] Data;
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}
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size_t getDepth() const { return Depth; }
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unsigned& operator[](size_t idx) const {
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// Depth is expected to be a power-of-2.
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assert(Depth && !(Depth & (Depth - 1)) &&
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"Scoreboard was not initialized properly!");
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return Data[(Head + idx) & (Depth-1)];
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}
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void reset(size_t d = 1) {
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if (Data == NULL) {
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Depth = d;
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Data = new unsigned[Depth];
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}
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memset(Data, 0, Depth * sizeof(Data[0]));
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Head = 0;
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}
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void advance() {
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Head = (Head + 1) & (Depth-1);
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}
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void recede() {
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Head = (Head - 1) & (Depth-1);
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}
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// Print the scoreboard.
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void dump() const;
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};
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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#ifndef NDEBUG
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// Support for tracing ScoreboardHazardRecognizer as a component within
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// another module. Follows the current thread-unsafe model of tracing.
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static const char *DebugType;
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#endif
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2010-06-14 21:06:53 +00:00
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// Itinerary data for the target.
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2010-09-10 01:29:16 +00:00
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const InstrItineraryData *ItinData;
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2010-06-14 21:06:53 +00:00
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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const ScheduleDAG *DAG;
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/// IssueWidth - Max issue per cycle. 0=Unknown.
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unsigned IssueWidth;
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/// IssueCount - Count instructions issued in this cycle.
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unsigned IssueCount;
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Scoreboard ReservedScoreboard;
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Scoreboard RequiredScoreboard;
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2010-06-14 21:06:53 +00:00
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public:
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
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const ScheduleDAG *DAG,
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const char *ParentDebugType = "");
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/// atIssueLimit - Return true if no more instructions may be issued in this
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/// cycle.
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virtual bool atIssueLimit() const;
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2010-06-14 21:06:53 +00:00
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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// Stalls provides an cycle offset at which SU will be scheduled. It will be
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// negative for bottom-up scheduling.
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virtual HazardType getHazardType(SUnit *SU, int Stalls);
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virtual void Reset();
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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virtual void RecedeCycle();
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};
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}
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2010-12-08 20:04:29 +00:00
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#endif //!LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
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