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https://github.com/c64scene-ar/llvm-6502.git
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106 lines
4.3 KiB
LLVM
106 lines
4.3 KiB
LLVM
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; RUN: llc < %s -regalloc=fast -verify-machineinstrs
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target triple = "arm-pc-linux-gnu"
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; This test case would accidentally use the same physreg for two virtregs
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; because allocVirtReg forgot to check if registers were already used in the
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; instruction.
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; This caused the RegScavenger to complain, but -verify-machineinstrs also
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; catches it.
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%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
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@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1]
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@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1]
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declare fastcc i32 @FirstOne()
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define fastcc void @Evaluate() {
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entry:
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br i1 false, label %cond_false186, label %cond_true
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cond_true: ; preds = %entry
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ret void
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cond_false186: ; preds = %entry
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br i1 false, label %cond_true293, label %bb203
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bb203: ; preds = %cond_false186
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ret void
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cond_true293: ; preds = %cond_false186
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br i1 false, label %cond_true298, label %cond_next317
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cond_true298: ; preds = %cond_true293
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br i1 false, label %cond_next518, label %cond_true397.preheader
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cond_next317: ; preds = %cond_true293
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ret void
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cond_true397.preheader: ; preds = %cond_true298
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ret void
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cond_next518: ; preds = %cond_true298
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br i1 false, label %bb1069, label %cond_true522
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cond_true522: ; preds = %cond_next518
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ret void
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bb1069: ; preds = %cond_next518
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br i1 false, label %cond_next1131, label %bb1096
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bb1096: ; preds = %bb1069
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ret void
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cond_next1131: ; preds = %bb1069
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br i1 false, label %cond_next1207, label %cond_true1150
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cond_true1150: ; preds = %cond_next1131
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ret void
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cond_next1207: ; preds = %cond_next1131
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br i1 false, label %cond_next1219, label %cond_true1211
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cond_true1211: ; preds = %cond_next1207
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ret void
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cond_next1219: ; preds = %cond_next1207
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br i1 false, label %cond_true1223, label %cond_next1283
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cond_true1223: ; preds = %cond_next1219
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br i1 false, label %cond_true1254, label %cond_true1264
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cond_true1254: ; preds = %cond_true1223
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br i1 false, label %bb1567, label %cond_true1369.preheader
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cond_true1264: ; preds = %cond_true1223
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ret void
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cond_next1283: ; preds = %cond_next1219
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ret void
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cond_true1369.preheader: ; preds = %cond_true1254
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ret void
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bb1567: ; preds = %cond_true1254
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%tmp1591 = load i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1]
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%tmp1572 = tail call fastcc i32 @FirstOne() ; <i32> [#uses=1]
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%tmp1594 = load i32* undef ; <i32> [#uses=1]
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%tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; <i8> [#uses=1]
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%shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1]
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%tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1]
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%tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1]
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%tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1]
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%gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1]
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%tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1]
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%tmp1599 = load i32* %tmp1598 ; <i32> [#uses=1]
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%tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1]
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br i1 undef, label %cond_next1637, label %cond_true1607
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cond_true1607: ; preds = %bb1567
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ret void
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cond_next1637: ; preds = %bb1567
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%tmp1662 = sub i32 %tmp1602, 0 ; <i32> [#uses=0]
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ret void
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}
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