2014-12-18 16:39:29 +00:00
|
|
|
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
|
|
|
|
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
|
|
|
|
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
|
|
|
|
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
|
|
|
|
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
|
|
|
|
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
|
|
|
|
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
|
|
|
|
; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; Keep one big-endian check so that we don't reduce testing, but don't add more
|
|
|
|
; since endianness doesn't affect the body of the atomic operations.
|
2014-12-18 16:39:29 +00:00
|
|
|
; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
@x = common global i32 0, align 4
|
|
|
|
|
2014-11-07 16:54:21 +00:00
|
|
|
define i32 @AtomicLoadAdd32(i32 signext %incr) nounwind {
|
2011-05-31 02:54:07 +00:00
|
|
|
entry:
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw add i32* @x, i32 %incr monotonic
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i32 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicLoadAdd32:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
|
|
|
|
; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
|
|
|
|
; ALL: sc $[[R2]], 0($[[R0]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
2014-11-07 16:54:21 +00:00
|
|
|
define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
|
2011-05-31 02:54:07 +00:00
|
|
|
entry:
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw nand i32* @x, i32 %incr monotonic
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i32 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicLoadNand32:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
|
|
|
|
; ALL: and $[[R3:[0-9]+]], $[[R1]], $4
|
|
|
|
; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
|
|
|
|
; ALL: sc $[[R2]], 0($[[R0]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
2014-11-07 16:54:21 +00:00
|
|
|
define i32 @AtomicSwap32(i32 signext %newval) nounwind {
|
2011-05-31 02:54:07 +00:00
|
|
|
entry:
|
2011-07-18 18:52:12 +00:00
|
|
|
%newval.addr = alloca i32, align 4
|
|
|
|
store i32 %newval, i32* %newval.addr, align 4
|
2015-02-27 21:17:42 +00:00
|
|
|
%tmp = load i32, i32* %newval.addr, align 4
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i32 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicSwap32:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll ${{[0-9]+}}, 0($[[R0]])
|
|
|
|
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
2014-11-07 16:54:21 +00:00
|
|
|
define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
|
2011-05-31 02:54:07 +00:00
|
|
|
entry:
|
2011-07-18 18:52:12 +00:00
|
|
|
%newval.addr = alloca i32, align 4
|
|
|
|
store i32 %newval, i32* %newval.addr, align 4
|
2015-02-27 21:17:42 +00:00
|
|
|
%tmp = load i32, i32* %newval.addr, align 4
|
2014-03-11 10:48:52 +00:00
|
|
|
%0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic
|
IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:07 +00:00
|
|
|
%1 = extractvalue { i32, i1 } %0, 0
|
|
|
|
ret i32 %1
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicCmpSwap32:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $2, 0($[[R0]])
|
|
|
|
; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
|
|
|
|
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: $[[BB1]]:
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@y = common global i8 0, align 1
|
|
|
|
|
|
|
|
define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
|
|
|
|
entry:
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw add i8* @y, i8 %incr monotonic
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i8 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicLoadAdd8:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
|
|
|
|
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
|
|
|
|
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
|
|
|
|
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
|
|
|
|
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
|
|
|
|
; ALL: ori $[[R6:[0-9]+]], $zero, 255
|
|
|
|
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
|
|
|
|
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
|
|
|
|
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
|
|
|
|
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
|
|
|
|
; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
|
|
|
|
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
|
|
|
|
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
|
|
|
|
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
|
|
|
|
; ALL: sc $[[R14]], 0($[[R2]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
|
2014-06-16 10:25:17 +00:00
|
|
|
|
|
|
|
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
|
|
|
|
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
|
|
|
|
; NO-SEB-SEH: sra $2, $[[R17]], 24
|
|
|
|
|
|
|
|
; HAS-SEB-SEH: seb $2, $[[R16]]
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
|
|
|
|
entry:
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw sub i8* @y, i8 %incr monotonic
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i8 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicLoadSub8:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
|
|
|
|
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
|
|
|
|
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
|
|
|
|
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
|
2013-05-31 03:25:44 +00:00
|
|
|
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: ori $[[R6:[0-9]+]], $zero, 255
|
|
|
|
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
|
|
|
|
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
|
|
|
|
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
|
|
|
|
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
|
|
|
|
; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
|
|
|
|
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
|
|
|
|
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
|
|
|
|
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
|
|
|
|
; ALL: sc $[[R14]], 0($[[R2]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
|
2014-06-16 10:25:17 +00:00
|
|
|
|
|
|
|
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
|
|
|
|
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
|
|
|
|
; NO-SEB-SEH: sra $2, $[[R17]], 24
|
|
|
|
|
|
|
|
; HAS-SEB-SEH:seb $2, $[[R16]]
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
|
|
|
|
entry:
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw nand i8* @y, i8 %incr monotonic
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i8 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicLoadNand8:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
|
|
|
|
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
|
|
|
|
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
|
|
|
|
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
|
|
|
|
; ALL: ori $[[R6:[0-9]+]], $zero, 255
|
|
|
|
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
|
|
|
|
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
|
|
|
|
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
|
|
|
|
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
|
|
|
|
; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
|
|
|
|
; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]]
|
|
|
|
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
|
|
|
|
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
|
|
|
|
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
|
|
|
|
; ALL: sc $[[R14]], 0($[[R2]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
|
2014-06-16 10:25:17 +00:00
|
|
|
|
|
|
|
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
|
|
|
|
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
|
|
|
|
; NO-SEB-SEH: sra $2, $[[R17]], 24
|
|
|
|
|
|
|
|
; HAS-SEB-SEH: seb $2, $[[R16]]
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
2011-07-18 18:52:12 +00:00
|
|
|
define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
|
2011-05-31 02:54:07 +00:00
|
|
|
entry:
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw xchg i8* @y, i8 %newval monotonic
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i8 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicSwap8:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
|
|
|
|
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
|
|
|
|
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
|
|
|
|
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
|
|
|
|
; ALL: ori $[[R6:[0-9]+]], $zero, 255
|
|
|
|
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
|
|
|
|
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
|
|
|
|
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
|
|
|
|
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
|
|
|
|
; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
|
|
|
|
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
|
|
|
|
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
|
|
|
|
; ALL: sc $[[R14]], 0($[[R2]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
|
2014-06-16 10:25:17 +00:00
|
|
|
|
|
|
|
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
|
|
|
|
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
|
|
|
|
; NO-SEB-SEH: sra $2, $[[R17]], 24
|
|
|
|
|
|
|
|
; HAS-SEB-SEH: seb $2, $[[R16]]
|
Replace the result usages while legalizing cmpxchg.
We should update the usages to all of the results;
otherwise, we might get assertion failure or SEGV during
the type legalization of ATOMIC_CMP_SWAP_WITH_SUCCESS
with two or more illegal types.
For example, in the following sequence, both i8 and i1
might be illegal in some target, e.g. armv5, mipsel, mips64el,
%0 = cmpxchg i8* %ptr, i8 %desire, i8 %new monotonic monotonic
%1 = extractvalue { i8, i1 } %0, 1
Since both i8 and i1 should be legalized, the corresponding
ATOMIC_CMP_SWAP_WITH_SUCCESS dag will be checked/replaced/updated
twice.
If we don't update the usage to *ALL* of the results in the
first round, the DAG for extractvalue might be processed earlier.
The GetPromotedInteger() will result in assertion failure,
because its operand (i.e. the success bit of cmpxchg) is not
promoted beforehand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:33:44 +00:00
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
|
|
|
|
entry:
|
IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:07 +00:00
|
|
|
%pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
|
|
|
|
%0 = extractvalue { i8, i1 } %pair0, 0
|
2011-05-31 02:54:07 +00:00
|
|
|
ret i8 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: AtomicCmpSwap8:
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(y)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(y)(
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
|
|
|
|
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
|
|
|
|
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
|
|
|
|
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
|
|
|
|
; ALL: ori $[[R6:[0-9]+]], $zero, 255
|
|
|
|
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
|
|
|
|
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
|
|
|
|
; ALL: andi $[[R9:[0-9]+]], $4, 255
|
|
|
|
; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
|
|
|
|
; ALL: andi $[[R11:[0-9]+]], $5, 255
|
|
|
|
; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
|
|
|
|
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
|
|
|
|
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
|
|
|
|
; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
|
|
|
|
|
|
|
|
; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
|
|
|
|
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
|
|
|
|
; ALL: sc $[[R16]], 0($[[R2]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R16]], $[[BB0]]
|
2014-06-16 10:25:17 +00:00
|
|
|
|
|
|
|
; ALL: $[[BB1]]:
|
|
|
|
; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
|
|
|
|
; NO-SEB-SEH: sra $2, $[[R18]], 24
|
|
|
|
|
|
|
|
; HAS-SEB-SEH: seb $2, $[[R17]]
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
2011-07-19 23:30:50 +00:00
|
|
|
|
2014-11-07 16:54:21 +00:00
|
|
|
define i1 @AtomicCmpSwapRes8(i8* %ptr, i8 signext %oldval, i8 signext %newval) nounwind {
|
Replace the result usages while legalizing cmpxchg.
We should update the usages to all of the results;
otherwise, we might get assertion failure or SEGV during
the type legalization of ATOMIC_CMP_SWAP_WITH_SUCCESS
with two or more illegal types.
For example, in the following sequence, both i8 and i1
might be illegal in some target, e.g. armv5, mipsel, mips64el,
%0 = cmpxchg i8* %ptr, i8 %desire, i8 %new monotonic monotonic
%1 = extractvalue { i8, i1 } %0, 1
Since both i8 and i1 should be legalized, the corresponding
ATOMIC_CMP_SWAP_WITH_SUCCESS dag will be checked/replaced/updated
twice.
If we don't update the usage to *ALL* of the results in the
first round, the DAG for extractvalue might be processed earlier.
The GetPromotedInteger() will result in assertion failure,
because its operand (i.e. the success bit of cmpxchg) is not
promoted beforehand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:33:44 +00:00
|
|
|
entry:
|
|
|
|
%0 = cmpxchg i8* %ptr, i8 %oldval, i8 %newval monotonic monotonic
|
|
|
|
%1 = extractvalue { i8, i1 } %0, 1
|
|
|
|
ret i1 %1
|
|
|
|
; ALL-LABEL: AtomicCmpSwapRes8
|
|
|
|
|
|
|
|
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
|
|
|
|
; ALL: and $[[R2:[0-9]+]], $4, $[[R1]]
|
|
|
|
; ALL: andi $[[R3:[0-9]+]], $4, 3
|
|
|
|
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
|
|
|
|
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
|
|
|
|
; ALL: ori $[[R6:[0-9]+]], $zero, 255
|
|
|
|
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
|
|
|
|
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
|
|
|
|
; ALL: andi $[[R9:[0-9]+]], $5, 255
|
|
|
|
; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
|
|
|
|
; ALL: andi $[[R11:[0-9]+]], $6, 255
|
|
|
|
; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
|
|
|
|
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
|
|
|
|
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
|
|
|
|
; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
|
|
|
|
|
|
|
|
; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
|
|
|
|
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
|
|
|
|
; ALL: sc $[[R16]], 0($[[R2]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R16]], $[[BB0]]
|
Replace the result usages while legalizing cmpxchg.
We should update the usages to all of the results;
otherwise, we might get assertion failure or SEGV during
the type legalization of ATOMIC_CMP_SWAP_WITH_SUCCESS
with two or more illegal types.
For example, in the following sequence, both i8 and i1
might be illegal in some target, e.g. armv5, mipsel, mips64el,
%0 = cmpxchg i8* %ptr, i8 %desire, i8 %new monotonic monotonic
%1 = extractvalue { i8, i1 } %0, 1
Since both i8 and i1 should be legalized, the corresponding
ATOMIC_CMP_SWAP_WITH_SUCCESS dag will be checked/replaced/updated
twice.
If we don't update the usage to *ALL* of the results in the
first round, the DAG for extractvalue might be processed earlier.
The GetPromotedInteger() will result in assertion failure,
because its operand (i.e. the success bit of cmpxchg) is not
promoted beforehand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213569 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 17:33:44 +00:00
|
|
|
|
|
|
|
; ALL: $[[BB1]]:
|
|
|
|
; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
|
|
|
|
|
|
|
|
; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
|
|
|
|
; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24
|
|
|
|
|
|
|
|
; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]]
|
|
|
|
|
|
|
|
; ALL: xor $[[R20:[0-9]+]], $[[R19]], $5
|
|
|
|
; ALL: sltiu $2, $[[R20]], 1
|
|
|
|
}
|
|
|
|
|
2014-06-16 13:13:03 +00:00
|
|
|
; Check one i16 so that we cover the seh sign extend
|
|
|
|
@z = common global i16 0, align 1
|
|
|
|
|
|
|
|
define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {
|
|
|
|
entry:
|
|
|
|
%0 = atomicrmw add i16* @z, i16 %incr monotonic
|
|
|
|
ret i16 %0
|
|
|
|
|
|
|
|
; ALL-LABEL: AtomicLoadAdd16:
|
|
|
|
|
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(z)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(z)(
|
|
|
|
|
|
|
|
; ALL: addiu $[[R1:[0-9]+]], $zero, -4
|
|
|
|
; ALL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
|
|
|
|
; ALL: andi $[[R3:[0-9]+]], $[[R0]], 3
|
|
|
|
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 2
|
|
|
|
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
|
|
|
|
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
|
|
|
|
; ALL: ori $[[R6:[0-9]+]], $zero, 65535
|
|
|
|
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
|
|
|
|
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
|
|
|
|
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
|
|
|
|
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
|
|
|
|
; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
|
|
|
|
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
|
|
|
|
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
|
|
|
|
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
|
|
|
|
; ALL: sc $[[R14]], 0($[[R2]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
|
|
|
|
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
|
|
|
|
|
|
|
|
; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 16
|
|
|
|
; NO-SEB-SEH: sra $2, $[[R17]], 16
|
|
|
|
|
|
|
|
; MIPS32R2: seh $2, $[[R16]]
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-07-19 23:30:50 +00:00
|
|
|
@countsint = common global i32 0, align 4
|
|
|
|
|
2014-11-07 16:54:21 +00:00
|
|
|
define i32 @CheckSync(i32 signext %v) nounwind noinline {
|
2011-07-19 23:30:50 +00:00
|
|
|
entry:
|
2011-09-26 20:27:49 +00:00
|
|
|
%0 = atomicrmw add i32* @countsint, i32 %v seq_cst
|
2011-07-19 23:30:50 +00:00
|
|
|
ret i32 %0
|
|
|
|
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL-LABEL: CheckSync:
|
|
|
|
|
2014-06-18 17:10:30 +00:00
|
|
|
; ALL: sync
|
2014-06-16 10:25:17 +00:00
|
|
|
; ALL: ll
|
|
|
|
; ALL: sc
|
|
|
|
; ALL: beq
|
2014-06-18 17:10:30 +00:00
|
|
|
; ALL: sync
|
2011-07-19 23:30:50 +00:00
|
|
|
}
|
|
|
|
|
2012-05-11 23:22:18 +00:00
|
|
|
; make sure that this assertion in
|
|
|
|
; TwoAddressInstructionPass::TryInstructionTransform does not fail:
|
|
|
|
;
|
|
|
|
; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) &&
|
|
|
|
;
|
|
|
|
; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an
|
|
|
|
; operand of an atomic instruction with register $zero.
|
|
|
|
@a = external global i32
|
|
|
|
|
|
|
|
define i32 @zeroreg() nounwind {
|
|
|
|
entry:
|
IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 14:24:07 +00:00
|
|
|
%pair0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst seq_cst
|
|
|
|
%0 = extractvalue { i32, i1 } %pair0, 0
|
2012-05-11 23:22:18 +00:00
|
|
|
%1 = icmp eq i32 %0, 1
|
|
|
|
%conv = zext i1 %1 to i32
|
|
|
|
ret i32 %conv
|
|
|
|
}
|
2014-06-16 13:13:03 +00:00
|
|
|
|
|
|
|
; Check that MIPS32R6 has the correct offset range.
|
|
|
|
; FIXME: At the moment, we don't seem to do addr+offset for any atomic load/store.
|
2014-11-07 16:54:21 +00:00
|
|
|
define i32 @AtomicLoadAdd32_OffGt9Bit(i32 signext %incr) nounwind {
|
2014-06-16 13:13:03 +00:00
|
|
|
entry:
|
2015-03-13 18:20:45 +00:00
|
|
|
%0 = atomicrmw add i32* getelementptr(i32, i32* @x, i32 256), i32 %incr monotonic
|
2014-06-16 13:13:03 +00:00
|
|
|
ret i32 %0
|
|
|
|
|
|
|
|
; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit:
|
|
|
|
|
|
|
|
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
|
|
|
|
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
|
|
|
|
|
|
|
|
; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024
|
|
|
|
; ALL: $[[BB0:[A-Z_0-9]+]]:
|
|
|
|
; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]])
|
|
|
|
; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
|
|
|
|
; ALL: sc $[[R2]], 0($[[PTR]])
|
2014-12-18 16:39:29 +00:00
|
|
|
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
|
|
|
|
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
|
2014-06-16 13:13:03 +00:00
|
|
|
}
|