llvm-6502/test/CodeGen/R600/hsa.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s

; HSA: {{^}}simple:
; HSA: .section        .hsa.version
; HSA-NEXT: .ascii  "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
; Make sure we are setting the ATC bit:
; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0

define void @simple(i32 addrspace(1)* %out) {
entry:
  store i32 0, i32 addrspace(1)* %out
  ret void
}
R600: Move DataLayout to AMDGPUTargetMachine This is a follow up to r227113. It is now required to use the amdgcn target for SI and newer GPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227316 91177308-0d34-0410-b5e6-96231b3b80d8 2015-01-28 16:04:26 +00:00			`; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri \| FileCheck --check-prefix=HSA %s`
R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223125 91177308-0d34-0410-b5e6-96231b3b80d8 2014-12-02 17:05:41 +00:00
			`; HSA: {{^}}simple:`
R600/SI: Emit .hsa.version section for amdhsa OS git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226970 91177308-0d34-0410-b5e6-96231b3b80d8 2015-01-23 23:59:08 +00:00			`; HSA: .section .hsa.version`
			`; HSA-NEXT: .ascii "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"`
R600/SI: Set the ATC bit on all resource descriptors for the HSA runtime git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223125 91177308-0d34-0410-b5e6-96231b3b80d8 2014-12-02 17:05:41 +00:00			`; Make sure we are setting the ATC bit:`
			`; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000`
			`; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0`

			`define void @simple(i32 addrspace(1)* %out) {`
			`entry:`
			`store i32 0, i32 addrspace(1)* %out`
			`ret void`
			`}`