2014-06-19 01:19:19 +00:00
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone
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declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone
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; SI-LABEL: @test_div_fixup_f32:
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; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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2014-09-24 02:14:26 +00:00
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; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]]
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; SI-DAG: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]]
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2014-06-19 01:19:19 +00:00
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; SI: V_DIV_FIXUP_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
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; SI: BUFFER_STORE_DWORD [[RESULT]],
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; SI: S_ENDPGM
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define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
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%result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @test_div_fixup_f64:
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; SI: V_DIV_FIXUP_F64
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define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind {
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%result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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