llvm-6502/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll

; RUN: llc < %s -march=ppc64

        %struct.TCMalloc_SpinLock = type { i32 }

define void @_ZN17TCMalloc_SpinLock4LockEv(%struct.TCMalloc_SpinLock* %this) {
entry:
        %tmp3 = call i32 asm sideeffect "1: lwarx $0, 0, $1\0A\09stwcx. $2, 0, $1\0A\09bne- 1b\0A\09isync", "=&r,=*r,r,1,~{dirflag},~{fpsr},~{flags},~{memory}"( i32** null, i32 1, i32* null )         ; <i32> [#uses=0]
        unreachable
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-09 00:09:15 +00:00			`; RUN: llc < %s -march=ppc64`
Sometimes a MI can define a register as well as defining a super-register at the same time. Do not mark the "smaller" def as dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41871 91177308-0d34-0410-b5e6-96231b3b80d8 2007-09-11 22:34:47 +00:00
			`%struct.TCMalloc_SpinLock = type { i32 }`

			`define void @_ZN17TCMalloc_SpinLock4LockEv(%struct.TCMalloc_SpinLock* %this) {`
			`entry:`
			`%tmp3 = call i32 asm sideeffect "1: lwarx $0, 0, $1\0A\09stwcx. $2, 0, $1\0A\09bne- 1b\0A\09isync", "=&r,=r,r,1,~{dirflag},~{fpsr},~{flags},~{memory}"( i32* null, i32 1, i32* null ) ; <i32> [#uses=0]`
			`unreachable`
			`}`