2007-06-06 07:42:06 +00:00
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//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-reg-info"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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2007-07-11 23:21:31 +00:00
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#include "MipsMachineFunction.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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//#include "MipsSubtarget.h"
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using namespace llvm;
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// TODO: add subtarget support
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MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
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: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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TII(tii) {}
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void MipsRegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, true)
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.addImm(0).addFrameIndex(FI);
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2007-06-06 07:42:06 +00:00
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else
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assert(0 && "Can't store this register to stack slot");
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}
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void MipsRegisterInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
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else
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assert(0 && "Can't load this register from stack slot");
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}
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void MipsRegisterInfo::
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
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.addReg(SrcReg);
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else
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assert (0 && "Can't copy this register");
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}
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void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const
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{
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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MachineInstr *MipsRegisterInfo::
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foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const
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{
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MachineInstr *NewMI = NULL;
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switch (MI->getOpcode())
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{
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case Mips::ADDu:
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if ((MI->getOperand(0).isRegister()) &&
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(MI->getOperand(1).isRegister()) &&
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(MI->getOperand(1).getReg() == Mips::ZERO) &&
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(MI->getOperand(2).isRegister()))
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{
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if (OpNum == 0) // COPY -> STORE
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NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
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.addImm(0).addReg(MI->getOperand(2).getReg());
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else // COPY -> LOAD
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NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
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.getReg()).addImm(0).addFrameIndex(FI);
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}
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break;
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}
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if (NewMI)
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NewMI->copyKillDeadInfo(MI);
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return NewMI;
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}
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/// Mips Callee Saved Registers
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const unsigned* MipsRegisterInfo::
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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getCalleeSavedRegs(const MachineFunction *MF) const
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2007-06-06 07:42:06 +00:00
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{
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// Mips calle-save register range is $16-$26(s0-s7)
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static const unsigned CalleeSavedRegs[] = {
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Mips::S0, Mips::S1, Mips::S2, Mips::S3,
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Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
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};
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return CalleeSavedRegs;
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}
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/// Mips Callee Saved Register Classes
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const TargetRegisterClass* const*
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
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2007-06-06 07:42:06 +00:00
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{
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
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};
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return CalleeSavedRegClasses;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const
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{
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BitVector Reserved(getNumRegs());
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Reserved.set(Mips::ZERO);
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Reserved.set(Mips::AT);
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Reserved.set(Mips::K0);
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Reserved.set(Mips::K1);
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Reserved.set(Mips::GP);
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Reserved.set(Mips::SP);
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Reserved.set(Mips::FP);
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Reserved.set(Mips::RA);
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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2007-07-11 23:21:31 +00:00
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//
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2007-06-06 07:42:06 +00:00
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// Stack Frame Processing methods
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2007-07-11 23:21:31 +00:00
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// +----------------------------+
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//
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// Too meet ABI, we construct the frame on the reverse
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// of natural order.
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//
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// The LLVM Frame will look like this:
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//
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// As the stack grows down, we start at 0, and the reference
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// is decrement.
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//
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// 0 ----------
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// -4 Args to pass
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// . saved "Callee Saved" Registers
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// . Local Area
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// . saved FP
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// . saved RA
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// -StackSize -----------
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//
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// On the EliminateFrameIndex we just negate the address above
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// and we get the stack frame required by the ABI, which is:
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//
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// sp + stacksize -------------
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// saved $RA (only on non-leaf functions)
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// saved $FP (only with frame pointer)
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// saved "Callee Saved" Registers
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// Local Area
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// saved $GP (used in PIC - not supported yet)
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// Args to pass area
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// sp -------------
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//
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// The sp is the stack pointer subtracted/added from the stack size
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// at the Prologue/Epilogue
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//
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// References to the previous stack (to obtain arguments) are done
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// with fixed location stack frames using positive stack offsets.
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//
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// Examples:
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// - reference to the actual stack frame
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// for any local area var there is smt like : FI >= 0, StackOffset: -4
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// sw REGX, 4(REGY)
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//
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// - reference to previous stack frame
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// suppose there's a store to the 5th arguments : FI < 0, StackOffset: 16.
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// The emitted instruction will be something like:
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// sw REGX, 16+StackSize (REGY)
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//
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//===----------------------------------------------------------------------===//
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2007-07-11 23:21:31 +00:00
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool MipsRegisterInfo::
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hasFP(const MachineFunction &MF) const {
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return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void MipsRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const
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{
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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unsigned i = 0;
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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int stackSize = MF.getFrameInfo()->getStackSize();
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int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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#ifndef NDEBUG
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DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
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DOUT << "<--------->\n";
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MI.print(DOUT);
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DOUT << "FrameIndex : " << FrameIndex << "\n";
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DOUT << "spOffset : " << spOffset << "\n";
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DOUT << "stackSize : " << stackSize << "\n";
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#endif
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2007-07-11 23:21:31 +00:00
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int Offset = ( (spOffset >= 0) ? (stackSize + spOffset) : (-spOffset));
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#ifndef NDEBUG
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DOUT << "Offset : " << Offset << "\n";
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DOUT << "<--------->\n";
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#endif
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MI.getOperand(i-1).ChangeToImmediate(Offset);
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MI.getOperand(i).ChangeToRegister(getFrameRegister(MF),false);
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2007-06-06 07:42:06 +00:00
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}
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void MipsRegisterInfo::
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emitPrologue(MachineFunction &MF) const
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{
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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2007-06-06 07:42:06 +00:00
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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2007-07-11 23:21:31 +00:00
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#ifndef NDEBUG
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DOUT << "\n<--- EMIT PROLOGUE --->";
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DOUT << "Stack size :" << NumBytes << "\n";
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#endif
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2007-06-06 07:42:06 +00:00
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// Do we need to allocate space on the stack?
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if (NumBytes == 0) return;
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2007-07-11 23:21:31 +00:00
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int FPOffset, RAOffset;
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// Always allocate space for saved RA and FP,
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// even if FramePointer is not used. When not
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// using FP, the last stack slot becomes empty
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// and RA is saved before it.
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if ((hasFP(MF)) && (MFI->hasCalls())) {
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FPOffset = NumBytes;
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RAOffset = (NumBytes+4);
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} else if ((!hasFP(MF)) && (MFI->hasCalls())) {
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FPOffset = 0;
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RAOffset = NumBytes;
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} else if ((hasFP(MF)) && (!MFI->hasCalls())) {
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FPOffset = NumBytes;
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RAOffset = 0;
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}
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MFI->setObjectOffset(MFI->CreateStackObject(4,4), -FPOffset);
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MFI->setObjectOffset(MFI->CreateStackObject(4,4), -RAOffset);
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MipsFI->setFPStackOffset(FPOffset);
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MipsFI->setRAStackOffset(RAOffset);
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#ifndef NDEBUG
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DOUT << "FPOffset :" << FPOffset << "\n";
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DOUT << "RAOffset :" << RAOffset << "\n";
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#endif
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// Align stack.
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NumBytes += 8;
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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NumBytes = ((NumBytes+Align-1)/Align*Align);
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#ifndef NDEBUG
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DOUT << "New stack size :" << NumBytes << "\n\n";
|
|
|
|
#endif
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2007-07-11 23:21:31 +00:00
|
|
|
// Update frame info
|
2007-06-06 07:42:06 +00:00
|
|
|
MFI->setStackSize(NumBytes);
|
|
|
|
|
2007-07-11 23:21:31 +00:00
|
|
|
// Adjust stack : addi sp, sp, (-imm)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
|
|
|
|
.addReg(Mips::SP).addImm(-NumBytes);
|
|
|
|
|
|
|
|
// Save the return address only if the function isnt a leaf one.
|
|
|
|
// sw $ra, stack_loc($sp)
|
|
|
|
if (MFI->hasCalls()) {
|
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::SW))
|
|
|
|
.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
|
|
|
|
}
|
|
|
|
|
|
|
|
// if framepointer enabled, save it and set it
|
|
|
|
// to point to the stack pointer
|
|
|
|
if (hasFP(MF)) {
|
|
|
|
// sw $fp,stack_loc($sp)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::SW))
|
|
|
|
.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
|
|
|
|
|
|
|
|
// move $fp, $sp
|
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
|
|
|
|
.addReg(Mips::SP).addReg(Mips::ZERO);
|
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void MipsRegisterInfo::
|
|
|
|
emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
|
|
|
|
{
|
|
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
2007-07-11 23:21:31 +00:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Get the number of bytes from FrameInfo
|
|
|
|
int NumBytes = (int) MFI->getStackSize();
|
|
|
|
|
2007-07-11 23:21:31 +00:00
|
|
|
// Get the FI's where RA and FP are saved.
|
|
|
|
int FPOffset = MipsFI->getFPStackOffset();
|
|
|
|
int RAOffset = MipsFI->getRAStackOffset();
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
DOUT << "\n<--- EMIT EPILOGUE --->" << "\n";
|
|
|
|
DOUT << "Stack size :" << NumBytes << "\n";
|
|
|
|
DOUT << "FPOffset :" << FPOffset << "\n";
|
|
|
|
DOUT << "RAOffset :" << RAOffset << "\n\n";
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// if framepointer enabled, restore it and restore the
|
|
|
|
// stack pointer
|
|
|
|
if (hasFP(MF)) {
|
|
|
|
// move $sp, $fp
|
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
|
|
|
|
.addReg(Mips::FP).addReg(Mips::ZERO);
|
|
|
|
|
|
|
|
// lw $fp,stack_loc($sp)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::LW))
|
|
|
|
.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Restore the return address only if the function isnt a leaf one.
|
|
|
|
// lw $ra, stack_loc($sp)
|
|
|
|
if (MFI->hasCalls()) {
|
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::LW))
|
|
|
|
.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// adjust stack : insert addi sp, sp, (imm)
|
|
|
|
if (NumBytes) {
|
2007-07-11 23:21:31 +00:00
|
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
|
|
|
|
.addReg(Mips::SP).addImm(NumBytes);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsRegisterInfo::
|
2007-07-11 23:21:31 +00:00
|
|
|
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
|
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
unsigned MipsRegisterInfo::
|
|
|
|
getRARegister() const {
|
|
|
|
return Mips::RA;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MipsRegisterInfo::
|
|
|
|
getFrameRegister(MachineFunction &MF) const {
|
2007-07-11 23:21:31 +00:00
|
|
|
return hasFP(MF) ? Mips::FP : Mips::SP;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MipsRegisterInfo::
|
|
|
|
getEHExceptionRegister() const {
|
|
|
|
assert(0 && "What is the exception register");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MipsRegisterInfo::
|
|
|
|
getEHHandlerRegister() const {
|
|
|
|
assert(0 && "What is the exception handler register");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#include "MipsGenRegisterInfo.inc"
|
|
|
|
|