2009-10-19 20:20:46 +00:00
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//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
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//
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2006-05-14 22:18:28 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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2006-05-14 22:18:28 +00:00
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format ARM assembly language.
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//
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//===----------------------------------------------------------------------===//
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2006-12-19 22:59:26 +00:00
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#define DEBUG_TYPE "asm-printer"
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2006-05-14 22:18:28 +00:00
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#include "ARM.h"
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2009-05-23 19:51:20 +00:00
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#include "ARMBuildAttrs.h"
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2007-01-19 07:51:42 +00:00
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#include "ARMAddressingModes.h"
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#include "ARMConstantPoolValue.h"
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2009-10-19 19:59:05 +00:00
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#include "ARMInstPrinter.h"
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2009-10-19 20:20:46 +00:00
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#include "ARMMachineFunctionInfo.h"
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#include "ARMMCInstLower.h"
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#include "ARMTargetMachine.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/Constants.h"
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#include "llvm/Module.h"
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2009-12-28 12:27:56 +00:00
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#include "llvm/Type.h"
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2009-08-13 01:36:44 +00:00
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#include "llvm/Assembly/Writer.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/CodeGen/AsmPrinter.h"
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2007-01-19 07:51:42 +00:00
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#include "llvm/CodeGen/DwarfWriter.h"
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2009-10-19 18:38:33 +00:00
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2007-01-19 07:51:42 +00:00
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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2009-10-19 18:38:33 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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2009-10-19 20:20:46 +00:00
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#include "llvm/MC/MCInst.h"
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2009-08-10 18:15:01 +00:00
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#include "llvm/MC/MCSectionMachO.h"
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2009-08-19 05:49:37 +00:00
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#include "llvm/MC/MCStreamer.h"
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2009-09-13 17:14:04 +00:00
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#include "llvm/MC/MCSymbol.h"
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2006-07-27 11:38:51 +00:00
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#include "llvm/Target/TargetData.h"
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2009-07-28 03:13:23 +00:00
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#include "llvm/Target/TargetLoweringObjectFile.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/Target/TargetMachine.h"
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2007-01-19 19:25:36 +00:00
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#include "llvm/Target/TargetOptions.h"
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2009-07-15 20:24:03 +00:00
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#include "llvm/Target/TargetRegistry.h"
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2009-07-24 18:19:46 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2009-09-01 18:49:12 +00:00
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#include "llvm/ADT/SmallString.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/ADT/Statistic.h"
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2009-11-06 23:33:28 +00:00
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#include "llvm/ADT/StringExtras.h"
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2008-12-05 01:06:39 +00:00
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#include "llvm/ADT/StringSet.h"
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2009-10-19 20:20:46 +00:00
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#include "llvm/Support/CommandLine.h"
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2009-07-08 20:55:50 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2009-10-19 20:20:46 +00:00
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#include "llvm/Support/FormattedStream.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/Support/MathExtras.h"
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#include <cctype>
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using namespace llvm;
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2006-12-19 22:59:26 +00:00
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STATISTIC(EmittedInsts, "Number of machine instrs printed");
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2006-05-14 22:18:28 +00:00
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2009-10-19 20:20:46 +00:00
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static cl::opt<bool>
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EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
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cl::desc("enable experimental asmprinter gunk in the arm backend"));
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2006-12-19 22:59:26 +00:00
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namespace {
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2009-10-19 17:59:19 +00:00
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class ARMAsmPrinter : public AsmPrinter {
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2007-01-19 07:51:42 +00:00
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when printing asm code for different targets.
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const ARMSubtarget *Subtarget;
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/// AFI - Keep a pointer to ARMFunctionInfo for the current
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2008-09-18 07:27:23 +00:00
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/// MachineFunction.
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2007-01-19 07:51:42 +00:00
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ARMFunctionInfo *AFI;
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2008-09-18 07:27:23 +00:00
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/// MCP - Keep a pointer to constantpool entries of the current
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/// MachineFunction.
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const MachineConstantPool *MCP;
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2009-02-24 08:30:20 +00:00
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public:
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2009-07-14 20:18:05 +00:00
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explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
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2009-08-22 20:48:53 +00:00
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const MCAsmInfo *T, bool V)
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2009-10-19 18:08:02 +00:00
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: AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
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2009-02-24 08:30:20 +00:00
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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}
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2006-05-14 22:18:28 +00:00
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virtual const char *getPassName() const {
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return "ARM Assembly Printer";
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}
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2009-10-19 19:59:05 +00:00
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void printMCInst(const MCInst *MI) {
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2009-10-19 21:21:39 +00:00
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ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
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2009-10-19 20:20:46 +00:00
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}
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void printInstructionThroughMCStreamer(const MachineInstr *MI);
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2006-05-14 22:18:28 +00:00
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2009-06-29 07:51:04 +00:00
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void printOperand(const MachineInstr *MI, int OpNum,
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2007-01-19 07:51:42 +00:00
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const char *Modifier = 0);
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2009-06-29 07:51:04 +00:00
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void printSOImmOperand(const MachineInstr *MI, int OpNum);
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void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
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void printSORegOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
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void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
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void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
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2007-01-19 07:51:42 +00:00
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const char *Modifier = 0);
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2009-06-29 07:51:04 +00:00
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void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
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2007-01-19 07:51:42 +00:00
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const char *Modifier = 0);
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2009-07-01 23:16:05 +00:00
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void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
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2009-06-29 07:51:04 +00:00
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void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
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2007-01-19 07:51:42 +00:00
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const char *Modifier = 0);
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2009-06-29 07:51:04 +00:00
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void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
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2009-06-27 02:26:13 +00:00
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2009-11-19 06:57:41 +00:00
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void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
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2009-07-09 23:43:36 +00:00
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void printThumbITMask(const MachineInstr *MI, int OpNum);
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2009-06-29 07:51:04 +00:00
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void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
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2007-01-19 07:51:42 +00:00
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unsigned Scale);
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2009-06-29 07:51:04 +00:00
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void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
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2009-06-27 02:26:13 +00:00
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void printT2SOOperand(const MachineInstr *MI, int OpNum);
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2009-06-29 07:51:04 +00:00
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void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
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2009-07-09 22:21:59 +00:00
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void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
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2009-07-02 07:28:31 +00:00
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void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
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2009-06-29 07:51:04 +00:00
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void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
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void printPredicateOperand(const MachineInstr *MI, int OpNum);
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void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
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void printPCLabel(const MachineInstr *MI, int OpNum);
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void printRegisterList(const MachineInstr *MI, int OpNum);
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void printCPInstOperand(const MachineInstr *MI, int OpNum,
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2007-01-19 07:51:42 +00:00
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const char *Modifier);
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2009-06-29 07:51:04 +00:00
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void printJTBlockOperand(const MachineInstr *MI, int OpNum);
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Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
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void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
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2009-07-29 02:18:14 +00:00
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void printTBAddrMode(const MachineInstr *MI, int OpNum);
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2009-08-21 21:58:55 +00:00
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void printNoHashImmediate(const MachineInstr *MI, int OpNum);
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2009-10-28 01:44:26 +00:00
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void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
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void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
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2007-01-19 07:51:42 +00:00
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2009-11-06 23:33:28 +00:00
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void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
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}
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void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
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}
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void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
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}
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void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
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}
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2009-06-29 07:51:04 +00:00
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virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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2007-01-19 07:51:42 +00:00
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unsigned AsmVariant, const char *ExtraCode);
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2009-06-29 07:51:04 +00:00
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virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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2009-05-19 05:53:42 +00:00
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unsigned AsmVariant,
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const char *ExtraCode);
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2006-05-14 22:18:28 +00:00
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2009-07-21 18:38:57 +00:00
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void PrintGlobalVariable(const GlobalVariable* GVar);
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2009-08-08 01:32:19 +00:00
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void printInstruction(const MachineInstr *MI); // autogenerated.
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2009-09-13 20:19:22 +00:00
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static const char *getRegisterName(unsigned RegNo);
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2009-09-13 20:08:00 +00:00
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2007-01-19 07:51:42 +00:00
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void printMachineInstruction(const MachineInstr *MI);
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2006-05-14 22:18:28 +00:00
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bool runOnMachineFunction(MachineFunction &F);
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2009-09-30 22:06:26 +00:00
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void EmitStartOfAsmFile(Module &M);
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2009-10-19 17:59:19 +00:00
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void EmitEndOfAsmFile(Module &M);
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2007-01-19 07:51:42 +00:00
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2008-08-08 06:56:16 +00:00
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/// EmitMachineConstantPoolValue - Print a machine constantpool value to
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/// the .s file.
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2007-01-19 07:51:42 +00:00
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virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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printDataDirective(MCPV->getType());
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2008-08-08 06:56:16 +00:00
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ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
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2010-01-13 06:38:18 +00:00
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SmallString<128> TmpNameStr;
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2009-09-01 01:57:56 +00:00
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if (ACPV->isLSDA()) {
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2010-01-13 06:38:18 +00:00
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raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
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2009-09-01 18:49:12 +00:00
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"_LSDA_" << getFunctionNumber();
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2010-01-13 06:38:18 +00:00
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O << TmpNameStr.str();
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2009-11-02 16:59:06 +00:00
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} else if (ACPV->isBlockAddress()) {
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2010-01-13 06:38:18 +00:00
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O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
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2009-11-02 16:59:06 +00:00
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} else if (ACPV->isGlobalValue()) {
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GlobalValue *GV = ACPV->getGV();
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2009-08-28 23:18:09 +00:00
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bool isIndirect = Subtarget->isTargetDarwin() &&
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2009-09-03 07:04:02 +00:00
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Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
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2009-08-28 23:18:09 +00:00
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if (!isIndirect)
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2010-01-15 23:26:49 +00:00
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GetGlobalValueSymbol(GV)->print(O, MAI);
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2009-08-28 23:18:09 +00:00
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else {
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// FIXME: Remove this when Darwin transition to @GOT like syntax.
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2010-01-16 18:37:32 +00:00
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MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
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2010-01-15 23:26:49 +00:00
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Sym->print(O, MAI);
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2009-10-19 18:49:14 +00:00
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MachineModuleInfoMachO &MMIMachO =
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MMI->getObjFileInfo<MachineModuleInfoMachO>();
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const MCSymbol *&StubSym =
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GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
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MMIMachO.getGVStubEntry(Sym);
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2010-01-15 23:26:49 +00:00
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if (StubSym == 0)
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2010-01-15 23:18:17 +00:00
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StubSym = GetGlobalValueSymbol(GV);
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2009-08-28 23:18:09 +00:00
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}
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2009-11-02 16:59:06 +00:00
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} else {
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assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
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2010-01-15 23:18:17 +00:00
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GetExternalSymbolSymbol(ACPV->getSymbol())->print(O, MAI);
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2009-11-02 16:59:06 +00:00
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}
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2009-09-04 01:38:51 +00:00
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2007-04-22 00:04:12 +00:00
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if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
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2007-04-27 13:54:47 +00:00
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if (ACPV->getPCAdjustment() != 0) {
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2009-08-22 21:43:10 +00:00
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O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
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2009-11-06 22:24:13 +00:00
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<< getFunctionNumber() << "_" << ACPV->getLabelId()
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2007-04-27 13:54:47 +00:00
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<< "+" << (unsigned)ACPV->getPCAdjustment();
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if (ACPV->mustAddCurrentAddress())
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O << "-.";
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2010-01-15 23:26:49 +00:00
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O << ')';
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2007-04-27 13:54:47 +00:00
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}
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2010-01-15 23:26:49 +00:00
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O << '\n';
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2007-01-19 07:51:42 +00:00
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}
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2009-09-04 01:38:51 +00:00
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2007-01-19 07:51:42 +00:00
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void getAnalysisUsage(AnalysisUsage &AU) const {
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2007-09-30 13:39:29 +00:00
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|
AsmPrinter::getAnalysisUsage(AU);
|
2007-01-19 07:51:42 +00:00
|
|
|
AU.setPreservesAll();
|
2007-01-26 21:22:28 +00:00
|
|
|
AU.addRequired<MachineModuleInfo>();
|
2009-01-08 23:40:34 +00:00
|
|
|
AU.addRequired<DwarfWriter>();
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
};
|
|
|
|
} // end of anonymous namespace
|
|
|
|
|
|
|
|
#include "ARMGenAsmWriter.inc"
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
/// runOnMachineFunction - This uses the printInstruction()
|
2006-05-14 22:18:28 +00:00
|
|
|
/// method to print assembly for each instruction.
|
|
|
|
///
|
|
|
|
bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
|
2009-02-24 08:30:20 +00:00
|
|
|
this->MF = &MF;
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
AFI = MF.getInfo<ARMFunctionInfo>();
|
2008-09-18 07:27:23 +00:00
|
|
|
MCP = MF.getConstantPool();
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
SetupMachineFunction(MF);
|
|
|
|
O << "\n";
|
|
|
|
|
|
|
|
// NOTE: we don't print out constant pools here, they are handled as
|
|
|
|
// instructions.
|
2006-05-23 02:48:20 +00:00
|
|
|
|
2009-08-03 22:32:50 +00:00
|
|
|
O << '\n';
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2006-05-23 02:48:20 +00:00
|
|
|
// Print out labels for the function.
|
|
|
|
const Function *F = MF.getFunction();
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
|
2009-08-03 22:32:50 +00:00
|
|
|
|
2006-05-23 02:48:20 +00:00
|
|
|
switch (F->getLinkage()) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unknown linkage type!");
|
2009-01-15 20:18:42 +00:00
|
|
|
case Function::PrivateLinkage:
|
2006-05-23 02:48:20 +00:00
|
|
|
case Function::InternalLinkage:
|
|
|
|
break;
|
|
|
|
case Function::ExternalLinkage:
|
2010-01-16 00:21:18 +00:00
|
|
|
O << "\t.globl\t";
|
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
O << "\n";
|
2006-05-23 02:48:20 +00:00
|
|
|
break;
|
2009-08-24 01:03:42 +00:00
|
|
|
case Function::LinkerPrivateLinkage:
|
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-07 15:45:40 +00:00
|
|
|
case Function::WeakAnyLinkage:
|
|
|
|
case Function::WeakODRLinkage:
|
|
|
|
case Function::LinkOnceAnyLinkage:
|
|
|
|
case Function::LinkOnceODRLinkage:
|
2007-01-19 19:25:36 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
2010-01-16 00:21:18 +00:00
|
|
|
O << "\t.globl\t";
|
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
O << "\n";
|
|
|
|
O << "\t.weak_definition\t";
|
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
O << "\n";
|
2007-01-19 07:51:42 +00:00
|
|
|
} else {
|
2010-01-16 00:21:18 +00:00
|
|
|
O << MAI->getWeakRefDirective();
|
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
O << "\n";
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-23 02:48:20 +00:00
|
|
|
break;
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2010-01-16 00:21:18 +00:00
|
|
|
printVisibility(CurrentFnSym, F->getVisibility());
|
2007-03-29 07:49:34 +00:00
|
|
|
|
2009-10-02 06:57:25 +00:00
|
|
|
unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
|
2007-01-19 07:51:42 +00:00
|
|
|
if (AFI->isThumbFunction()) {
|
2009-10-02 06:57:25 +00:00
|
|
|
EmitAlignment(FnAlign, F, AFI->getAlign());
|
2007-01-19 07:51:42 +00:00
|
|
|
O << "\t.code\t16\n";
|
2007-02-01 18:25:34 +00:00
|
|
|
O << "\t.thumb_func";
|
2010-01-16 00:21:18 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
O << "\t";
|
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
}
|
2007-02-01 18:25:34 +00:00
|
|
|
O << "\n";
|
2009-06-30 22:38:32 +00:00
|
|
|
} else {
|
2009-10-02 06:57:25 +00:00
|
|
|
EmitAlignment(FnAlign, F);
|
2009-06-30 22:38:32 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2010-01-16 00:21:18 +00:00
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
O << ":\n";
|
2007-05-03 20:28:35 +00:00
|
|
|
// Emit pre-function debug information.
|
2009-01-08 23:40:34 +00:00
|
|
|
DW->BeginFunction(&MF);
|
2006-05-23 02:48:20 +00:00
|
|
|
|
2008-01-28 09:15:03 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
// If the function is empty, then we need to emit *something*. Otherwise,
|
|
|
|
// the function's label might be associated with something that it wasn't
|
|
|
|
// meant to be associated with. We emit a noop in this situation.
|
|
|
|
MachineFunction::iterator I = MF.begin();
|
|
|
|
|
|
|
|
if (++I == MF.end() && MF.front().empty())
|
|
|
|
O << "\tnop\n";
|
|
|
|
}
|
|
|
|
|
2006-05-23 02:48:20 +00:00
|
|
|
// Print out code for the function.
|
|
|
|
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
|
|
|
|
I != E; ++I) {
|
|
|
|
// Print a label for the basic block.
|
2009-10-19 20:20:46 +00:00
|
|
|
if (I != MF.begin())
|
2009-09-13 18:25:37 +00:00
|
|
|
EmitBasicBlockStart(I);
|
2009-10-19 20:20:46 +00:00
|
|
|
|
|
|
|
// Print the assembly for the instruction.
|
2006-05-23 02:48:20 +00:00
|
|
|
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
|
2009-10-19 20:20:46 +00:00
|
|
|
II != E; ++II)
|
2007-01-19 07:51:42 +00:00
|
|
|
printMachineInstruction(II);
|
2006-09-11 17:25:40 +00:00
|
|
|
}
|
|
|
|
|
2010-01-16 00:21:18 +00:00
|
|
|
if (MAI->hasDotTypeDotSizeDirective()) {
|
|
|
|
O << "\t.size ";
|
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
O << ", .-";
|
|
|
|
CurrentFnSym->print(O, MAI);
|
|
|
|
O << "\n";
|
|
|
|
}
|
2006-11-08 17:07:32 +00:00
|
|
|
|
2007-05-03 20:28:35 +00:00
|
|
|
// Emit post-function debug information.
|
2009-01-08 23:40:34 +00:00
|
|
|
DW->EndFunction(&MF);
|
2006-10-17 18:04:53 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
return false;
|
2006-10-17 18:04:53 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
|
2007-01-19 07:51:42 +00:00
|
|
|
const char *Modifier) {
|
2009-06-29 07:51:04 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
2009-11-24 00:44:37 +00:00
|
|
|
unsigned TF = MO.getTargetFlags();
|
|
|
|
|
2006-05-25 12:57:06 +00:00
|
|
|
switch (MO.getType()) {
|
2009-10-19 20:59:55 +00:00
|
|
|
default:
|
|
|
|
assert(0 && "<unknown operand type>");
|
2009-06-22 23:27:02 +00:00
|
|
|
case MachineOperand::MO_Register: {
|
|
|
|
unsigned Reg = MO.getReg();
|
2009-10-19 20:59:55 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
|
|
|
|
if (Modifier && strcmp(Modifier, "dregpair") == 0) {
|
|
|
|
unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
|
|
|
|
unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
|
|
|
|
O << '{'
|
|
|
|
<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
|
|
|
|
<< '}';
|
|
|
|
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
|
|
|
|
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
|
|
|
|
unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
|
|
|
|
&ARM::DPR_VFP2RegClass);
|
|
|
|
O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
|
|
|
|
} else {
|
2009-11-07 15:20:32 +00:00
|
|
|
assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
2009-10-19 20:59:55 +00:00
|
|
|
O << getRegisterName(Reg);
|
|
|
|
}
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2009-06-22 23:27:02 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
case MachineOperand::MO_Immediate: {
|
2009-09-28 09:14:39 +00:00
|
|
|
int64_t Imm = MO.getImm();
|
2009-10-08 20:43:22 +00:00
|
|
|
O << '#';
|
2009-11-24 00:44:37 +00:00
|
|
|
if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
|
|
|
|
(TF & ARMII::MO_LO16))
|
|
|
|
O << ":lower16:";
|
|
|
|
else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
|
|
|
|
(TF & ARMII::MO_HI16))
|
|
|
|
O << ":upper16:";
|
2009-10-08 20:43:22 +00:00
|
|
|
O << Imm;
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-25 12:57:06 +00:00
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
2009-09-13 17:14:04 +00:00
|
|
|
GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
|
2006-05-25 12:57:06 +00:00
|
|
|
return;
|
2006-07-16 01:02:57 +00:00
|
|
|
case MachineOperand::MO_GlobalAddress: {
|
2007-01-19 07:51:42 +00:00
|
|
|
bool isCallOp = Modifier && !strcmp(Modifier, "call");
|
2006-07-16 01:02:57 +00:00
|
|
|
GlobalValue *GV = MO.getGlobal();
|
2009-11-24 00:44:37 +00:00
|
|
|
|
|
|
|
if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
|
|
|
|
(TF & ARMII::MO_LO16))
|
|
|
|
O << ":lower16:";
|
|
|
|
else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
|
|
|
|
(TF & ARMII::MO_HI16))
|
|
|
|
O << ":upper16:";
|
2010-01-15 23:26:49 +00:00
|
|
|
GetGlobalValueSymbol(GV)->print(O, MAI);
|
2008-11-22 16:15:34 +00:00
|
|
|
|
|
|
|
printOffset(MO.getOffset());
|
|
|
|
|
2007-04-22 00:04:12 +00:00
|
|
|
if (isCallOp && Subtarget->isTargetELF() &&
|
|
|
|
TM.getRelocationModel() == Reloc::PIC_)
|
|
|
|
O << "(PLT)";
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
case MachineOperand::MO_ExternalSymbol: {
|
|
|
|
bool isCallOp = Modifier && !strcmp(Modifier, "call");
|
2010-01-15 23:31:55 +00:00
|
|
|
GetExternalSymbolSymbol(MO.getSymbolName())->print(O, MAI);
|
2010-01-13 08:08:33 +00:00
|
|
|
|
2007-04-22 00:04:12 +00:00
|
|
|
if (isCallOp && Subtarget->isTargetELF() &&
|
|
|
|
TM.getRelocationModel() == Reloc::PIC_)
|
|
|
|
O << "(PLT)";
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-25 12:57:06 +00:00
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
|
2007-12-30 23:10:15 +00:00
|
|
|
<< '_' << MO.getIndex();
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
2007-12-30 23:10:15 +00:00
|
|
|
<< '_' << MO.getIndex();
|
2007-01-19 07:51:42 +00:00
|
|
|
break;
|
2006-05-25 12:57:06 +00:00
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2009-07-14 20:18:05 +00:00
|
|
|
static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
|
2009-08-22 21:43:10 +00:00
|
|
|
const MCAsmInfo *MAI) {
|
2009-07-08 21:03:57 +00:00
|
|
|
// Break it up into two parts that make up a shifter immediate.
|
|
|
|
V = ARM_AM::getSOImmVal(V);
|
|
|
|
assert(V != -1 && "Not a valid so_imm value!");
|
|
|
|
|
2007-03-20 08:11:30 +00:00
|
|
|
unsigned Imm = ARM_AM::getSOImmValImm(V);
|
|
|
|
unsigned Rot = ARM_AM::getSOImmValRot(V);
|
2008-11-22 16:15:34 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// Print low-level immediate formation info, per
|
|
|
|
// A5.1.3: "Data-processing operands - Immediate".
|
|
|
|
if (Rot) {
|
|
|
|
O << "#" << Imm << ", " << Rot;
|
|
|
|
// Pretty printed version.
|
2009-10-28 01:44:26 +00:00
|
|
|
if (VerboseAsm) {
|
|
|
|
O.PadToColumn(MAI->getCommentColumn());
|
|
|
|
O << MAI->getCommentString() << ' ';
|
|
|
|
O << (int)ARM_AM::rotr32(Imm, Rot);
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
} else {
|
|
|
|
O << "#" << Imm;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-20 08:11:30 +00:00
|
|
|
/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
|
|
|
|
/// immediate in bits 0-7.
|
|
|
|
void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
2008-10-03 15:45:36 +00:00
|
|
|
assert(MO.isImm() && "Not a valid so_imm value!");
|
2009-08-22 21:43:10 +00:00
|
|
|
printSOImm(O, MO.getImm(), VerboseAsm, MAI);
|
2007-03-20 08:11:30 +00:00
|
|
|
}
|
|
|
|
|
2008-11-06 02:25:39 +00:00
|
|
|
/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
|
|
|
|
/// followed by an 'orr' to materialize.
|
2007-03-20 08:11:30 +00:00
|
|
|
void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
2008-10-03 15:45:36 +00:00
|
|
|
assert(MO.isImm() && "Not a valid so_imm value!");
|
2007-12-30 20:49:49 +00:00
|
|
|
unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
|
|
|
|
unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
|
2009-08-22 21:43:10 +00:00
|
|
|
printSOImm(O, V1, VerboseAsm, MAI);
|
2007-06-05 18:55:18 +00:00
|
|
|
O << "\n\torr";
|
|
|
|
printPredicateOperand(MI, 2);
|
2009-10-26 23:45:59 +00:00
|
|
|
O << "\t";
|
2009-09-04 01:38:51 +00:00
|
|
|
printOperand(MI, 0);
|
2007-03-20 08:11:30 +00:00
|
|
|
O << ", ";
|
2009-09-04 01:38:51 +00:00
|
|
|
printOperand(MI, 0);
|
2007-03-20 08:11:30 +00:00
|
|
|
O << ", ";
|
2009-08-22 21:43:10 +00:00
|
|
|
printSOImm(O, V2, VerboseAsm, MAI);
|
2007-03-20 08:11:30 +00:00
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// so_reg is a 4-operand unit corresponding to register forms of the A5.1
|
|
|
|
// "Addressing Mode 1 - Data-processing operands" forms. This includes:
|
2009-06-27 02:26:13 +00:00
|
|
|
// REG 0 0 - e.g. R5
|
|
|
|
// REG REG 0,SH_OPC - e.g. R5, ROR R3
|
2007-01-19 07:51:42 +00:00
|
|
|
// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
|
|
|
|
void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << getRegisterName(MO1.getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
// Print the shift opc.
|
|
|
|
O << ", "
|
2007-12-30 20:49:49 +00:00
|
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
|
2007-01-19 07:51:42 +00:00
|
|
|
<< " ";
|
|
|
|
|
|
|
|
if (MO2.getReg()) {
|
2009-09-13 20:31:40 +00:00
|
|
|
O << getRegisterName(MO2.getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
|
|
|
|
} else {
|
|
|
|
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
|
2008-10-03 15:45:36 +00:00
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
2007-01-19 07:51:42 +00:00
|
|
|
printOperand(MI, Op);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
if (!MO2.getReg()) {
|
|
|
|
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
|
|
|
|
O << ", #"
|
|
|
|
<< (char)ARM_AM::getAM2Op(MO3.getImm())
|
|
|
|
<< ARM_AM::getAM2Offset(MO3.getImm());
|
|
|
|
O << "]";
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
O << ", "
|
|
|
|
<< (char)ARM_AM::getAM2Op(MO3.getImm())
|
2009-09-13 20:31:40 +00:00
|
|
|
<< getRegisterName(MO2.getReg());
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
|
|
|
|
O << ", "
|
2007-12-30 20:49:49 +00:00
|
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
|
2007-01-19 07:51:42 +00:00
|
|
|
<< " #" << ShImm;
|
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
|
|
|
|
if (!MO1.getReg()) {
|
2007-05-03 23:30:36 +00:00
|
|
|
unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
|
|
|
|
assert(ImmOffs && "Malformed indexed load / store!");
|
|
|
|
O << "#"
|
|
|
|
<< (char)ARM_AM::getAM2Op(MO2.getImm())
|
|
|
|
<< ImmOffs;
|
2007-01-19 07:51:42 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
O << (char)ARM_AM::getAM2Op(MO2.getImm())
|
2009-09-13 20:31:40 +00:00
|
|
|
<< getRegisterName(MO1.getReg());
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
|
|
|
|
O << ", "
|
2007-12-30 20:49:49 +00:00
|
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
|
2007-01-19 07:51:42 +00:00
|
|
|
<< " #" << ShImm;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2008-02-10 18:45:23 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
if (MO2.getReg()) {
|
|
|
|
O << ", "
|
|
|
|
<< (char)ARM_AM::getAM3Op(MO3.getImm())
|
2009-09-13 20:31:40 +00:00
|
|
|
<< getRegisterName(MO2.getReg())
|
2007-01-19 07:51:42 +00:00
|
|
|
<< "]";
|
|
|
|
return;
|
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
|
|
|
|
O << ", #"
|
|
|
|
<< (char)ARM_AM::getAM3Op(MO3.getImm())
|
|
|
|
<< ImmOffs;
|
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
|
|
|
|
if (MO1.getReg()) {
|
|
|
|
O << (char)ARM_AM::getAM3Op(MO2.getImm())
|
2009-09-13 20:31:40 +00:00
|
|
|
<< getRegisterName(MO1.getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
|
2007-05-03 23:30:36 +00:00
|
|
|
assert(ImmOffs && "Malformed indexed load / store!");
|
2007-01-19 07:51:42 +00:00
|
|
|
O << "#"
|
2007-05-03 23:30:36 +00:00
|
|
|
<< (char)ARM_AM::getAM3Op(MO2.getImm())
|
2007-01-19 07:51:42 +00:00
|
|
|
<< ImmOffs;
|
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
|
|
|
|
const char *Modifier) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
|
|
|
|
if (Modifier && strcmp(Modifier, "submode") == 0) {
|
|
|
|
if (MO1.getReg() == ARM::SP) {
|
2009-08-04 01:43:45 +00:00
|
|
|
// FIXME
|
2007-01-19 07:51:42 +00:00
|
|
|
bool isLDM = (MI->getOpcode() == ARM::LDM ||
|
2009-08-04 01:43:45 +00:00
|
|
|
MI->getOpcode() == ARM::LDM_RET ||
|
2009-08-04 21:12:13 +00:00
|
|
|
MI->getOpcode() == ARM::t2LDM ||
|
2009-08-04 01:43:45 +00:00
|
|
|
MI->getOpcode() == ARM::t2LDM_RET);
|
2007-01-19 07:51:42 +00:00
|
|
|
O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
|
|
|
|
} else
|
|
|
|
O << ARM_AM::getAMSubModeStr(Mode);
|
2009-08-07 21:19:10 +00:00
|
|
|
} else if (Modifier && strcmp(Modifier, "wide") == 0) {
|
|
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
|
|
|
|
if (Mode == ARM_AM::ia)
|
|
|
|
O << ".w";
|
2007-01-19 07:51:42 +00:00
|
|
|
} else {
|
|
|
|
printOperand(MI, Op);
|
|
|
|
if (ARM_AM::getAM4WBFlag(MO2.getImm()))
|
|
|
|
O << "!";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
|
|
|
|
const char *Modifier) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
|
2008-10-03 15:45:36 +00:00
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
2007-01-19 07:51:42 +00:00
|
|
|
printOperand(MI, Op);
|
|
|
|
return;
|
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2008-02-10 18:45:23 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
if (Modifier && strcmp(Modifier, "submode") == 0) {
|
|
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
|
2009-11-09 00:11:35 +00:00
|
|
|
O << ARM_AM::getAMSubModeStr(Mode);
|
2007-01-19 07:51:42 +00:00
|
|
|
return;
|
|
|
|
} else if (Modifier && strcmp(Modifier, "base") == 0) {
|
|
|
|
// Used for FSTM{D|S} and LSTM{D|S} operations.
|
2009-09-13 20:31:40 +00:00
|
|
|
O << getRegisterName(MO1.getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
|
|
|
|
O << "!";
|
|
|
|
return;
|
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
|
|
|
|
O << ", #"
|
|
|
|
<< (char)ARM_AM::getAM5Op(MO2.getImm())
|
|
|
|
<< ImmOffs*4;
|
|
|
|
}
|
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
2009-07-01 23:16:05 +00:00
|
|
|
void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
2009-11-07 21:25:39 +00:00
|
|
|
const MachineOperand &MO4 = MI->getOperand(Op+3);
|
2009-07-01 23:16:05 +00:00
|
|
|
|
2009-11-07 21:25:39 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
if (MO4.getImm()) {
|
2009-11-17 20:04:59 +00:00
|
|
|
// FIXME: Both darwin as and GNU as violate ARM docs here.
|
|
|
|
O << ", :" << MO4.getImm();
|
2009-11-07 21:25:39 +00:00
|
|
|
}
|
|
|
|
O << "]";
|
2009-07-01 23:16:05 +00:00
|
|
|
|
|
|
|
if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
|
|
|
|
if (MO2.getReg() == 0)
|
|
|
|
O << "!";
|
|
|
|
else
|
2009-09-13 20:31:40 +00:00
|
|
|
O << ", " << getRegisterName(MO2.getReg());
|
2009-07-01 23:16:05 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
|
|
|
|
const char *Modifier) {
|
|
|
|
if (Modifier && strcmp(Modifier, "label") == 0) {
|
|
|
|
printPCLabel(MI, Op+1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
2008-02-10 18:45:23 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2009-06-23 17:48:47 +00:00
|
|
|
void
|
|
|
|
ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(Op);
|
|
|
|
uint32_t v = ~MO.getImm();
|
2009-06-25 22:04:44 +00:00
|
|
|
int32_t lsb = CountTrailingZeros_32(v);
|
2009-06-24 01:08:42 +00:00
|
|
|
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
|
2009-06-23 17:48:47 +00:00
|
|
|
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
|
|
|
|
O << "#" << lsb << ", #" << width;
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
2009-11-19 06:57:41 +00:00
|
|
|
void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
|
|
|
|
O << "#" << MI->getOperand(Op).getImm() * 4;
|
|
|
|
}
|
|
|
|
|
2009-07-09 23:43:36 +00:00
|
|
|
void
|
|
|
|
ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
|
|
|
|
// (3 - the number of trailing zeros) is the number of then / else.
|
|
|
|
unsigned Mask = MI->getOperand(Op).getImm();
|
|
|
|
unsigned NumTZ = CountTrailingZeros_32(Mask);
|
|
|
|
assert(NumTZ <= 3 && "Invalid IT mask!");
|
2009-07-10 01:54:42 +00:00
|
|
|
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
|
2009-08-15 07:59:10 +00:00
|
|
|
bool T = (Mask & (1 << Pos)) == 0;
|
2009-07-09 23:43:36 +00:00
|
|
|
if (T)
|
|
|
|
O << 't';
|
|
|
|
else
|
|
|
|
O << 'e';
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
void
|
|
|
|
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
O << ", " << getRegisterName(MO2.getReg()) << "]";
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
|
|
|
|
unsigned Scale) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
2007-01-30 02:35:32 +00:00
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-10-03 15:45:36 +00:00
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
2007-01-19 07:51:42 +00:00
|
|
|
printOperand(MI, Op);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2007-01-30 02:35:32 +00:00
|
|
|
if (MO3.getReg())
|
2009-09-13 20:31:40 +00:00
|
|
|
O << ", " << getRegisterName(MO3.getReg());
|
2009-11-10 19:48:13 +00:00
|
|
|
else if (unsigned ImmOffs = MO2.getImm())
|
2009-11-19 06:31:26 +00:00
|
|
|
O << ", #+" << ImmOffs * Scale;
|
2007-01-19 07:51:42 +00:00
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2007-01-23 22:59:13 +00:00
|
|
|
ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
|
2007-01-30 02:35:32 +00:00
|
|
|
printThumbAddrModeRI5Operand(MI, Op, 1);
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
void
|
2007-01-23 22:59:13 +00:00
|
|
|
ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
|
2007-01-30 02:35:32 +00:00
|
|
|
printThumbAddrModeRI5Operand(MI, Op, 2);
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
void
|
2007-01-23 22:59:13 +00:00
|
|
|
ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
|
2007-01-30 02:35:32 +00:00
|
|
|
printThumbAddrModeRI5Operand(MI, Op, 4);
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2007-01-19 07:51:42 +00:00
|
|
|
if (unsigned ImmOffs = MO2.getImm())
|
2009-11-19 06:31:26 +00:00
|
|
|
O << ", #+" << ImmOffs*4;
|
2007-01-19 07:51:42 +00:00
|
|
|
O << "]";
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
2009-06-27 02:26:13 +00:00
|
|
|
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
|
|
|
|
// register with shift forms.
|
|
|
|
// REG 0 0 - e.g. R5
|
|
|
|
// REG IMM, SH_OPC - e.g. R5, LSL #3
|
|
|
|
void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
|
|
|
|
unsigned Reg = MO1.getReg();
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
|
2009-09-13 20:31:40 +00:00
|
|
|
O << getRegisterName(Reg);
|
2009-06-27 02:26:13 +00:00
|
|
|
|
|
|
|
// Print the shift opc.
|
|
|
|
O << ", "
|
|
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
|
|
|
|
<< " ";
|
|
|
|
|
|
|
|
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
|
|
|
|
O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
|
|
|
|
int OpNum) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2009-06-29 07:51:04 +00:00
|
|
|
|
|
|
|
unsigned OffImm = MO2.getImm();
|
|
|
|
if (OffImm) // Don't print +0.
|
|
|
|
O << ", #+" << OffImm;
|
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
|
|
|
|
int OpNum) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2009-06-29 07:51:04 +00:00
|
|
|
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
|
|
// Don't print +0.
|
|
|
|
if (OffImm < 0)
|
|
|
|
O << ", #-" << -OffImm;
|
|
|
|
else if (OffImm > 0)
|
|
|
|
O << ", #+" << OffImm;
|
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
2009-07-09 22:21:59 +00:00
|
|
|
void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
|
|
|
|
int OpNum) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2009-07-09 22:21:59 +00:00
|
|
|
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm() / 4;
|
|
|
|
// Don't print +0.
|
|
|
|
if (OffImm < 0)
|
2009-11-19 06:31:26 +00:00
|
|
|
O << ", #-" << -OffImm * 4;
|
2009-07-09 22:21:59 +00:00
|
|
|
else if (OffImm > 0)
|
2009-11-19 06:31:26 +00:00
|
|
|
O << ", #+" << OffImm * 4;
|
2009-07-09 22:21:59 +00:00
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
2009-07-02 07:28:31 +00:00
|
|
|
void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
|
|
|
|
int OpNum) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
int32_t OffImm = (int32_t)MO1.getImm();
|
|
|
|
// Don't print +0.
|
|
|
|
if (OffImm < 0)
|
|
|
|
O << "#-" << -OffImm;
|
|
|
|
else if (OffImm > 0)
|
|
|
|
O << "#+" << OffImm;
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
|
|
|
|
int OpNum) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
|
|
|
|
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
2009-06-29 07:51:04 +00:00
|
|
|
|
2009-08-11 08:52:18 +00:00
|
|
|
assert(MO2.getReg() && "Invalid so_reg load / store address!");
|
2009-09-13 20:31:40 +00:00
|
|
|
O << ", " << getRegisterName(MO2.getReg());
|
2009-06-27 02:26:13 +00:00
|
|
|
|
2009-08-11 08:52:18 +00:00
|
|
|
unsigned ShAmt = MO3.getImm();
|
|
|
|
if (ShAmt) {
|
|
|
|
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
|
|
|
|
O << ", lsl #" << ShAmt;
|
2009-06-29 07:51:04 +00:00
|
|
|
}
|
|
|
|
O << "]";
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
|
|
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
|
2007-05-15 01:29:07 +00:00
|
|
|
if (CC != ARMCC::AL)
|
|
|
|
O << ARMCondCodeToString(CC);
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
|
|
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
2007-07-06 01:01:34 +00:00
|
|
|
if (Reg) {
|
|
|
|
assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
|
|
|
|
O << 's';
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
|
|
|
|
int Id = (int)MI->getOperand(OpNum).getImm();
|
2009-11-06 22:24:13 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix()
|
|
|
|
<< "PC" << getFunctionNumber() << "_" << Id;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
|
2007-01-19 07:51:42 +00:00
|
|
|
O << "{";
|
2009-10-01 01:33:39 +00:00
|
|
|
// Always skip the first operand, it's the optional (and implicit writeback).
|
|
|
|
for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
|
2009-08-11 21:11:32 +00:00
|
|
|
if (MI->getOperand(i).isImplicit())
|
|
|
|
continue;
|
2009-10-01 01:33:39 +00:00
|
|
|
if ((int)i != OpNum+1) O << ", ";
|
2007-01-19 07:51:42 +00:00
|
|
|
printOperand(MI, i);
|
|
|
|
}
|
|
|
|
O << "}";
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
|
2007-01-19 07:51:42 +00:00
|
|
|
const char *Modifier) {
|
|
|
|
assert(Modifier && "This operand only works with a modifier!");
|
|
|
|
// There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
|
|
|
|
// data itself.
|
|
|
|
if (!strcmp(Modifier, "label")) {
|
2009-06-29 07:51:04 +00:00
|
|
|
unsigned ID = MI->getOperand(OpNum).getImm();
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
|
2007-10-14 05:57:21 +00:00
|
|
|
<< '_' << ID << ":\n";
|
2007-01-19 07:51:42 +00:00
|
|
|
} else {
|
|
|
|
assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
|
2009-06-29 07:51:04 +00:00
|
|
|
unsigned CPI = MI->getOperand(OpNum).getIndex();
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-09-18 07:27:23 +00:00
|
|
|
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2008-08-08 06:56:16 +00:00
|
|
|
if (MCPE.isMachineConstantPoolEntry()) {
|
2007-01-19 07:51:42 +00:00
|
|
|
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
|
2008-08-08 06:56:16 +00:00
|
|
|
} else {
|
2007-01-19 07:51:42 +00:00
|
|
|
EmitGlobalConstant(MCPE.Val.ConstVal);
|
2007-04-25 14:50:40 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
2007-12-30 23:10:15 +00:00
|
|
|
unsigned JTI = MO1.getIndex();
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
2007-12-30 20:49:49 +00:00
|
|
|
<< '_' << JTI << '_' << MO2.getImm() << ":\n";
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2009-08-22 21:43:10 +00:00
|
|
|
const char *JTEntryDirective = MAI->getData32bitsDirective();
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
const MachineFunction *MF = MI->getParent()->getParent();
|
2008-07-07 20:06:06 +00:00
|
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
2007-01-19 07:51:42 +00:00
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
2009-08-22 21:43:10 +00:00
|
|
|
bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
|
2009-07-24 18:19:46 +00:00
|
|
|
SmallPtrSet<MachineBasicBlock*, 8> JTSets;
|
2007-01-19 07:51:42 +00:00
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
bool isNew = JTSets.insert(MBB);
|
|
|
|
|
|
|
|
if (UseSet && isNew)
|
|
|
|
printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
O << JTEntryDirective << ' ';
|
|
|
|
if (UseSet)
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
|
2007-12-30 20:49:49 +00:00
|
|
|
<< '_' << JTI << '_' << MO2.getImm()
|
2007-10-14 05:57:21 +00:00
|
|
|
<< "_set_" << MBB->getNumber();
|
2007-01-19 07:51:42 +00:00
|
|
|
else if (TM.getRelocationModel() == Reloc::PIC_) {
|
2009-09-13 17:14:04 +00:00
|
|
|
GetMBBSymbol(MBB->getNumber())->print(O, MAI);
|
2009-08-22 21:43:10 +00:00
|
|
|
O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
|
2009-08-11 20:30:58 +00:00
|
|
|
<< getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
|
2009-07-24 18:19:46 +00:00
|
|
|
} else {
|
2009-09-13 17:14:04 +00:00
|
|
|
GetMBBSymbol(MBB->getNumber())->print(O, MAI);
|
2009-07-24 18:19:46 +00:00
|
|
|
}
|
2007-01-27 02:29:45 +00:00
|
|
|
if (i != e-1)
|
|
|
|
O << '\n';
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
|
|
unsigned JTI = MO1.getIndex();
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
<< '_' << JTI << '_' << MO2.getImm() << ":\n";
|
|
|
|
|
|
|
|
const MachineFunction *MF = MI->getParent()->getParent();
|
|
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
2009-07-29 02:18:14 +00:00
|
|
|
bool ByteOffset = false, HalfWordOffset = false;
|
|
|
|
if (MI->getOpcode() == ARM::t2TBB)
|
|
|
|
ByteOffset = true;
|
|
|
|
else if (MI->getOpcode() == ARM::t2TBH)
|
|
|
|
HalfWordOffset = true;
|
|
|
|
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
2009-07-29 02:18:14 +00:00
|
|
|
if (ByteOffset)
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getData8bitsDirective();
|
2009-07-29 02:18:14 +00:00
|
|
|
else if (HalfWordOffset)
|
2009-08-22 21:43:10 +00:00
|
|
|
O << MAI->getData16bitsDirective();
|
2009-07-29 02:18:14 +00:00
|
|
|
if (ByteOffset || HalfWordOffset) {
|
|
|
|
O << '(';
|
2009-09-13 17:14:04 +00:00
|
|
|
GetMBBSymbol(MBB->getNumber())->print(O, MAI);
|
2009-08-22 21:43:10 +00:00
|
|
|
O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
2009-07-29 02:18:14 +00:00
|
|
|
<< '_' << JTI << '_' << MO2.getImm() << ")/2";
|
|
|
|
} else {
|
|
|
|
O << "\tb.w ";
|
2009-09-13 17:14:04 +00:00
|
|
|
GetMBBSymbol(MBB->getNumber())->print(O, MAI);
|
2009-07-29 02:18:14 +00:00
|
|
|
}
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
if (i != e-1)
|
|
|
|
O << '\n';
|
|
|
|
}
|
2009-07-31 18:35:56 +00:00
|
|
|
|
|
|
|
// Make sure the instruction that follows TBB is 2-byte aligned.
|
|
|
|
// FIXME: Constant island pass should insert an "ALIGN" instruction instead.
|
|
|
|
if (ByteOffset && (JTBBs.size() & 1)) {
|
|
|
|
O << '\n';
|
|
|
|
EmitAlignment(1);
|
|
|
|
}
|
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-25 00:33:29 +00:00
|
|
|
}
|
|
|
|
|
2009-07-29 02:18:14 +00:00
|
|
|
void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
|
2009-07-29 02:18:14 +00:00
|
|
|
if (MI->getOpcode() == ARM::t2TBH)
|
|
|
|
O << ", lsl #1";
|
|
|
|
O << ']';
|
|
|
|
}
|
|
|
|
|
2009-08-21 21:58:55 +00:00
|
|
|
void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
|
2009-08-08 23:10:41 +00:00
|
|
|
O << MI->getOperand(OpNum).getImm();
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2009-10-28 01:44:26 +00:00
|
|
|
void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
|
|
|
|
const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
|
2009-11-23 21:08:25 +00:00
|
|
|
O << '#' << FP->getValueAPF().convertToFloat();
|
2009-10-28 01:44:26 +00:00
|
|
|
if (VerboseAsm) {
|
|
|
|
O.PadToColumn(MAI->getCommentColumn());
|
|
|
|
O << MAI->getCommentString() << ' ';
|
|
|
|
WriteAsOperand(O, FP, /*PrintType=*/false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
|
|
|
|
const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
|
2009-11-23 21:08:25 +00:00
|
|
|
O << '#' << FP->getValueAPF().convertToDouble();
|
2009-10-28 01:44:26 +00:00
|
|
|
if (VerboseAsm) {
|
|
|
|
O.PadToColumn(MAI->getCommentColumn());
|
|
|
|
O << MAI->getCommentString() << ' ';
|
|
|
|
WriteAsOperand(O, FP, /*PrintType=*/false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
2007-01-19 07:51:42 +00:00
|
|
|
unsigned AsmVariant, const char *ExtraCode){
|
|
|
|
// Does this asm operand have a single letter operand modifier?
|
|
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
2009-08-08 23:10:41 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
switch (ExtraCode[0]) {
|
|
|
|
default: return true; // Unknown modifier.
|
2009-07-09 23:54:51 +00:00
|
|
|
case 'a': // Print as a memory address.
|
|
|
|
if (MI->getOperand(OpNum).isReg()) {
|
2009-09-13 20:31:40 +00:00
|
|
|
O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
|
2009-07-09 23:54:51 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// Fallthrough
|
|
|
|
case 'c': // Don't print "#" before an immediate operand.
|
2009-08-21 21:58:55 +00:00
|
|
|
if (!MI->getOperand(OpNum).isImm())
|
|
|
|
return true;
|
|
|
|
printNoHashImmediate(MI, OpNum);
|
2009-04-06 21:46:51 +00:00
|
|
|
return false;
|
2007-04-04 00:13:29 +00:00
|
|
|
case 'P': // Print a VFP double precision register.
|
2009-12-08 23:06:22 +00:00
|
|
|
case 'q': // Print a NEON quad precision register.
|
2009-06-29 07:51:04 +00:00
|
|
|
printOperand(MI, OpNum);
|
2007-03-08 22:42:46 +00:00
|
|
|
return false;
|
2007-01-19 07:51:42 +00:00
|
|
|
case 'Q':
|
|
|
|
if (TM.getTargetData()->isLittleEndian())
|
|
|
|
break;
|
|
|
|
// Fallthrough
|
|
|
|
case 'R':
|
|
|
|
if (TM.getTargetData()->isBigEndian())
|
|
|
|
break;
|
|
|
|
// Fallthrough
|
2009-09-04 01:38:51 +00:00
|
|
|
case 'H': // Write second word of DI / DF reference.
|
2007-01-19 07:51:42 +00:00
|
|
|
// Verify that this operand has two consecutive registers.
|
2009-06-29 07:51:04 +00:00
|
|
|
if (!MI->getOperand(OpNum).isReg() ||
|
|
|
|
OpNum+1 == MI->getNumOperands() ||
|
|
|
|
!MI->getOperand(OpNum+1).isReg())
|
2007-01-19 07:51:42 +00:00
|
|
|
return true;
|
2009-06-29 07:51:04 +00:00
|
|
|
++OpNum; // Return the high-part.
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
printOperand(MI, OpNum);
|
2007-01-19 07:51:42 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-05-19 05:53:42 +00:00
|
|
|
bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
2009-06-29 07:51:04 +00:00
|
|
|
unsigned OpNum, unsigned AsmVariant,
|
2009-05-19 05:53:42 +00:00
|
|
|
const char *ExtraCode) {
|
|
|
|
if (ExtraCode && ExtraCode[0])
|
|
|
|
return true; // Unknown modifier.
|
2009-10-13 20:50:28 +00:00
|
|
|
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
|
|
|
O << "[" << getRegisterName(MO.getReg()) << "]";
|
2009-05-19 05:53:42 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
|
|
|
|
++EmittedInsts;
|
|
|
|
|
|
|
|
// Call the autogenerated instruction printer routines.
|
2009-10-06 02:19:11 +00:00
|
|
|
processDebugLoc(MI, true);
|
2009-10-19 20:20:46 +00:00
|
|
|
|
|
|
|
if (EnableMCInst) {
|
|
|
|
printInstructionThroughMCStreamer(MI);
|
|
|
|
} else {
|
2009-10-19 22:33:05 +00:00
|
|
|
int Opc = MI->getOpcode();
|
|
|
|
if (Opc == ARM::CONSTPOOL_ENTRY)
|
|
|
|
EmitAlignment(2);
|
|
|
|
|
2009-10-19 20:20:46 +00:00
|
|
|
printInstruction(MI);
|
|
|
|
}
|
|
|
|
|
2009-11-13 21:34:57 +00:00
|
|
|
if (VerboseAsm)
|
2009-09-09 23:14:36 +00:00
|
|
|
EmitComments(*MI);
|
|
|
|
O << '\n';
|
2009-10-06 02:19:11 +00:00
|
|
|
processDebugLoc(MI, false);
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2009-09-30 22:06:26 +00:00
|
|
|
void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
|
2009-09-30 00:23:42 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
Reloc::Model RelocM = TM.getRelocationModel();
|
|
|
|
if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
|
|
|
|
// Declare all the text sections up front (before the DWARF sections
|
|
|
|
// emitted by AsmPrinter::doInitialization) so the assembler will keep
|
|
|
|
// them together at the beginning of the object file. This helps
|
|
|
|
// avoid out-of-range branches that are due a fundamental limitation of
|
|
|
|
// the way symbol offsets are encoded with the current Darwin ARM
|
|
|
|
// relocations.
|
2009-09-30 22:25:37 +00:00
|
|
|
TargetLoweringObjectFileMachO &TLOFMacho =
|
|
|
|
static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
|
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getTextSection());
|
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
|
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
|
|
|
|
if (RelocM == Reloc::DynamicNoPIC) {
|
|
|
|
const MCSection *sect =
|
|
|
|
TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
|
|
|
|
MCSectionMachO::S_SYMBOL_STUBS,
|
|
|
|
12, SectionKind::getText());
|
|
|
|
OutStreamer.SwitchSection(sect);
|
|
|
|
} else {
|
|
|
|
const MCSection *sect =
|
|
|
|
TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
|
|
|
|
MCSectionMachO::S_SYMBOL_STUBS,
|
|
|
|
16, SectionKind::getText());
|
|
|
|
OutStreamer.SwitchSection(sect);
|
|
|
|
}
|
2009-09-30 00:23:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-11-09 00:11:35 +00:00
|
|
|
// Use unified assembler syntax.
|
|
|
|
O << "\t.syntax unified\n";
|
2009-06-17 23:43:18 +00:00
|
|
|
|
2009-05-23 19:51:20 +00:00
|
|
|
// Emit ARM Build Attributes
|
|
|
|
if (Subtarget->isTargetELF()) {
|
|
|
|
// CPU Type
|
2009-06-01 19:03:17 +00:00
|
|
|
std::string CPUString = Subtarget->getCPUString();
|
|
|
|
if (CPUString != "generic")
|
|
|
|
O << "\t.cpu " << CPUString << '\n';
|
2009-05-23 19:51:20 +00:00
|
|
|
|
|
|
|
// FIXME: Emit FPU type
|
|
|
|
if (Subtarget->hasVFP2())
|
|
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
|
|
|
|
|
|
|
|
// Signal various FP modes.
|
|
|
|
if (!UnsafeFPMath)
|
|
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
|
|
|
|
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
|
|
|
|
|
|
|
|
if (FiniteOnlyFPMath())
|
|
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
|
|
|
|
else
|
|
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
|
|
|
|
|
|
|
|
// 8-bytes alignment stuff.
|
|
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
|
|
|
|
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
|
|
|
|
|
2009-08-05 19:04:42 +00:00
|
|
|
// Hard float. Use both S and D registers and conform to AAPCS-VFP.
|
|
|
|
if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
|
|
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
|
|
|
|
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
|
|
|
|
|
2009-05-23 19:51:20 +00:00
|
|
|
// FIXME: Should we signal R9 usage?
|
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2009-07-21 18:38:57 +00:00
|
|
|
void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
|
2006-07-27 11:38:51 +00:00
|
|
|
const TargetData *TD = TM.getTargetData();
|
|
|
|
|
2008-08-07 09:54:23 +00:00
|
|
|
if (!GVar->hasInitializer()) // External global require no code
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Check to see if this is a special global used by LLVM, if so, emit it.
|
|
|
|
|
|
|
|
if (EmitSpecialLLVMGlobal(GVar)) {
|
|
|
|
if (Subtarget->isTargetDarwin() &&
|
|
|
|
TM.getRelocationModel() == Reloc::Static) {
|
2009-07-25 23:55:21 +00:00
|
|
|
if (GVar->getName() == "llvm.global_ctors")
|
2008-08-07 09:54:23 +00:00
|
|
|
O << ".reference .constructors_used\n";
|
2009-07-25 23:55:21 +00:00
|
|
|
else if (GVar->getName() == "llvm.global_dtors")
|
2008-08-07 09:54:23 +00:00
|
|
|
O << ".reference .destructors_used\n";
|
2007-01-30 08:04:53 +00:00
|
|
|
}
|
2008-08-07 09:54:23 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-01-15 23:31:55 +00:00
|
|
|
MCSymbol *GVarSym = GetGlobalValueSymbol(GVar);
|
|
|
|
|
2008-08-07 09:54:23 +00:00
|
|
|
Constant *C = GVar->getInitializer();
|
|
|
|
const Type *Type = C->getType();
|
2009-05-09 07:06:46 +00:00
|
|
|
unsigned Size = TD->getTypeAllocSize(Type);
|
2008-08-07 09:54:23 +00:00
|
|
|
unsigned Align = TD->getPreferredAlignmentLog(GVar);
|
2008-12-06 02:00:55 +00:00
|
|
|
bool isDarwin = Subtarget->isTargetDarwin();
|
2006-07-27 11:38:51 +00:00
|
|
|
|
2010-01-15 23:38:51 +00:00
|
|
|
printVisibility(GVarSym, GVar->getVisibility());
|
2007-04-30 00:23:51 +00:00
|
|
|
|
2010-01-15 23:31:55 +00:00
|
|
|
if (Subtarget->isTargetELF()) {
|
|
|
|
O << "\t.type ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << ",%object\n";
|
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2009-07-31 18:48:30 +00:00
|
|
|
const MCSection *TheSection =
|
2009-07-29 05:09:30 +00:00
|
|
|
getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(TheSection);
|
2007-04-30 00:23:51 +00:00
|
|
|
|
2009-07-27 05:32:16 +00:00
|
|
|
// FIXME: get this stuff from section kind flags.
|
2009-02-18 02:19:52 +00:00
|
|
|
if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
|
2009-07-24 04:08:17 +00:00
|
|
|
// Don't put things that should go in the cstring section into "comm".
|
2009-07-27 05:32:16 +00:00
|
|
|
!TheSection->getKind().isMergeableCString()) {
|
2008-08-07 09:54:23 +00:00
|
|
|
if (GVar->hasExternalLinkage()) {
|
2009-08-22 21:43:10 +00:00
|
|
|
if (const char *Directive = MAI->getZeroFillDirective()) {
|
2010-01-15 23:31:55 +00:00
|
|
|
O << "\t.globl\t";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "\n";
|
|
|
|
O << Directive << "__DATA, __common, ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << ", " << Size << ", " << Align << "\n";
|
2008-08-07 09:54:23 +00:00
|
|
|
return;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2007-01-19 19:25:36 +00:00
|
|
|
}
|
2006-12-08 21:24:58 +00:00
|
|
|
|
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-07 15:45:40 +00:00
|
|
|
if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
|
2008-08-07 09:54:23 +00:00
|
|
|
if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
|
|
|
|
|
2008-12-06 02:00:55 +00:00
|
|
|
if (isDarwin) {
|
2009-01-15 20:18:42 +00:00
|
|
|
if (GVar->hasLocalLinkage()) {
|
2010-01-15 23:31:55 +00:00
|
|
|
O << MAI->getLCOMMDirective();
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << ',' << Size << ',' << Align;
|
2008-12-06 02:00:55 +00:00
|
|
|
} else if (GVar->hasCommonLinkage()) {
|
2010-01-15 23:31:55 +00:00
|
|
|
O << MAI->getCOMMDirective();
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << ',' << Size << ',' << Align;
|
2008-12-06 02:00:55 +00:00
|
|
|
} else {
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(TheSection);
|
2010-01-15 23:31:55 +00:00
|
|
|
O << "\t.globl ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << '\n' << MAI->getWeakDefDirective();
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << '\n';
|
2008-12-06 02:00:55 +00:00
|
|
|
EmitAlignment(Align, GVar);
|
2010-01-15 23:31:55 +00:00
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << ":";
|
2009-03-24 00:17:40 +00:00
|
|
|
if (VerboseAsm) {
|
2009-10-28 01:44:26 +00:00
|
|
|
O.PadToColumn(MAI->getCommentColumn());
|
|
|
|
O << MAI->getCommentString() << ' ';
|
2009-08-13 01:36:44 +00:00
|
|
|
WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
|
2009-03-24 00:17:40 +00:00
|
|
|
}
|
2008-12-06 02:00:55 +00:00
|
|
|
O << '\n';
|
|
|
|
EmitGlobalConstant(C);
|
|
|
|
return;
|
|
|
|
}
|
2009-08-22 21:43:10 +00:00
|
|
|
} else if (MAI->getLCOMMDirective() != NULL) {
|
2009-01-15 20:18:42 +00:00
|
|
|
if (GVar->hasLocalLinkage()) {
|
2010-01-15 23:31:55 +00:00
|
|
|
O << MAI->getLCOMMDirective();
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "," << Size;
|
2008-12-06 02:00:55 +00:00
|
|
|
} else {
|
2010-01-15 23:31:55 +00:00
|
|
|
O << MAI->getCOMMDirective();
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "," << Size;
|
2009-08-22 21:43:10 +00:00
|
|
|
if (MAI->getCOMMDirectiveTakesAlignment())
|
|
|
|
O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
|
2008-12-06 02:00:55 +00:00
|
|
|
}
|
2007-01-19 19:25:36 +00:00
|
|
|
} else {
|
2010-01-15 23:31:55 +00:00
|
|
|
if (GVar->hasLocalLinkage()) {
|
|
|
|
O << "\t.local\t";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << '\n';
|
|
|
|
}
|
|
|
|
O << MAI->getCOMMDirective();
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "," << Size;
|
2009-08-22 21:43:10 +00:00
|
|
|
if (MAI->getCOMMDirectiveTakesAlignment())
|
|
|
|
O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
|
2007-01-19 19:25:36 +00:00
|
|
|
}
|
2009-03-24 00:17:40 +00:00
|
|
|
if (VerboseAsm) {
|
2009-10-28 01:44:26 +00:00
|
|
|
O.PadToColumn(MAI->getCommentColumn());
|
|
|
|
O << MAI->getCommentString() << ' ';
|
2009-08-13 01:36:44 +00:00
|
|
|
WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
|
2009-03-24 00:17:40 +00:00
|
|
|
}
|
2008-08-07 09:54:23 +00:00
|
|
|
O << "\n";
|
|
|
|
return;
|
2007-01-19 19:25:36 +00:00
|
|
|
}
|
2008-08-07 09:54:23 +00:00
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2008-08-07 09:54:23 +00:00
|
|
|
switch (GVar->getLinkage()) {
|
2009-07-24 03:49:17 +00:00
|
|
|
case GlobalValue::CommonLinkage:
|
|
|
|
case GlobalValue::LinkOnceAnyLinkage:
|
|
|
|
case GlobalValue::LinkOnceODRLinkage:
|
|
|
|
case GlobalValue::WeakAnyLinkage:
|
|
|
|
case GlobalValue::WeakODRLinkage:
|
2009-08-24 01:03:42 +00:00
|
|
|
case GlobalValue::LinkerPrivateLinkage:
|
2008-12-06 02:00:55 +00:00
|
|
|
if (isDarwin) {
|
2010-01-15 23:31:55 +00:00
|
|
|
O << "\t.globl ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "\n\t.weak_definition ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "\n";
|
2008-08-07 09:54:23 +00:00
|
|
|
} else {
|
2010-01-15 23:31:55 +00:00
|
|
|
O << "\t.weak ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "\n";
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2008-08-07 09:54:23 +00:00
|
|
|
break;
|
2009-07-24 03:49:17 +00:00
|
|
|
case GlobalValue::AppendingLinkage:
|
|
|
|
// FIXME: appending linkage variables should go into a section of
|
|
|
|
// their name or something. For now, just emit them as external.
|
|
|
|
case GlobalValue::ExternalLinkage:
|
2010-01-15 23:31:55 +00:00
|
|
|
O << "\t.globl ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << "\n";
|
2008-08-07 09:54:23 +00:00
|
|
|
break;
|
2009-07-24 03:49:17 +00:00
|
|
|
case GlobalValue::PrivateLinkage:
|
|
|
|
case GlobalValue::InternalLinkage:
|
|
|
|
break;
|
|
|
|
default:
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("Unknown linkage type!");
|
2008-08-07 09:54:23 +00:00
|
|
|
}
|
2006-07-27 11:38:51 +00:00
|
|
|
|
2008-08-07 09:54:23 +00:00
|
|
|
EmitAlignment(Align, GVar);
|
2010-01-15 23:31:55 +00:00
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << ":";
|
2009-03-24 00:17:40 +00:00
|
|
|
if (VerboseAsm) {
|
2009-10-28 01:44:26 +00:00
|
|
|
O.PadToColumn(MAI->getCommentColumn());
|
|
|
|
O << MAI->getCommentString() << ' ';
|
2009-08-13 01:36:44 +00:00
|
|
|
WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
|
2009-03-24 00:17:40 +00:00
|
|
|
}
|
2008-08-07 09:54:23 +00:00
|
|
|
O << "\n";
|
2010-01-15 23:31:55 +00:00
|
|
|
if (MAI->hasDotTypeDotSizeDirective()) {
|
|
|
|
O << "\t.size ";
|
|
|
|
GVarSym->print(O, MAI);
|
|
|
|
O << ", " << Size << "\n";
|
|
|
|
}
|
2008-08-07 09:54:23 +00:00
|
|
|
|
|
|
|
EmitGlobalConstant(C);
|
|
|
|
O << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-10-19 17:59:19 +00:00
|
|
|
void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
2007-01-19 19:25:36 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
2009-08-03 22:18:15 +00:00
|
|
|
// All darwin targets use mach-o.
|
2009-09-04 01:38:51 +00:00
|
|
|
TargetLoweringObjectFileMachO &TLOFMacho =
|
2009-08-03 22:18:15 +00:00
|
|
|
static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
|
2009-10-19 18:38:33 +00:00
|
|
|
MachineModuleInfoMachO &MMIMacho =
|
|
|
|
MMI->getObjFileInfo<MachineModuleInfoMachO>();
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2009-07-15 04:12:33 +00:00
|
|
|
O << '\n';
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
// Output non-lazy-pointers for external and common global variables.
|
2009-10-19 18:38:33 +00:00
|
|
|
MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
|
|
|
|
|
|
|
|
if (!Stubs.empty()) {
|
2009-08-10 01:39:42 +00:00
|
|
|
// Switch with ".non_lazy_symbol_pointer" directive.
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
|
2009-08-10 18:01:34 +00:00
|
|
|
EmitAlignment(2);
|
2009-10-19 18:38:33 +00:00
|
|
|
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
|
|
|
|
Stubs[i].first->print(O, MAI);
|
|
|
|
O << ":\n\t.indirect_symbol ";
|
|
|
|
Stubs[i].second->print(O, MAI);
|
|
|
|
O << "\n\t.long\t0\n";
|
2008-12-05 01:06:39 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2009-10-19 18:44:38 +00:00
|
|
|
Stubs = MMIMacho.GetHiddenGVStubList();
|
|
|
|
if (!Stubs.empty()) {
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
|
2009-08-10 18:02:16 +00:00
|
|
|
EmitAlignment(2);
|
2009-10-19 18:44:38 +00:00
|
|
|
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
|
|
|
|
Stubs[i].first->print(O, MAI);
|
|
|
|
O << ":\n\t.long ";
|
|
|
|
Stubs[i].second->print(O, MAI);
|
|
|
|
O << "\n";
|
2008-12-05 01:06:39 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// Funny Darwin hack: This flag tells the linker that no global symbols
|
|
|
|
// contain code that falls through to other global symbols (e.g. the obvious
|
|
|
|
// implementation of multiple entry points). If this doesn't occur, the
|
|
|
|
// linker can safely perform dead code stripping. Since LLVM never
|
|
|
|
// generates code that does this, it is always safe to set.
|
2009-10-19 18:03:08 +00:00
|
|
|
OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
|
2006-07-27 11:38:51 +00:00
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
2008-08-17 13:55:10 +00:00
|
|
|
|
2009-10-19 20:20:46 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
|
2009-10-20 00:52:47 +00:00
|
|
|
ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
|
2009-10-19 20:20:46 +00:00
|
|
|
switch (MI->getOpcode()) {
|
2009-10-20 05:58:02 +00:00
|
|
|
case ARM::t2MOVi32imm:
|
|
|
|
assert(0 && "Should be lowered by thumb2it pass");
|
2009-10-19 22:23:04 +00:00
|
|
|
default: break;
|
2009-10-19 20:20:46 +00:00
|
|
|
case TargetInstrInfo::DBG_LABEL:
|
|
|
|
case TargetInstrInfo::EH_LABEL:
|
|
|
|
case TargetInstrInfo::GC_LABEL:
|
|
|
|
printLabel(MI);
|
|
|
|
return;
|
|
|
|
case TargetInstrInfo::KILL:
|
2009-11-04 19:24:37 +00:00
|
|
|
printKill(MI);
|
2009-10-19 20:20:46 +00:00
|
|
|
return;
|
|
|
|
case TargetInstrInfo::INLINEASM:
|
|
|
|
printInlineAsm(MI);
|
|
|
|
return;
|
|
|
|
case TargetInstrInfo::IMPLICIT_DEF:
|
|
|
|
printImplicitDef(MI);
|
|
|
|
return;
|
2009-10-19 22:23:04 +00:00
|
|
|
case ARM::PICADD: { // FIXME: Remove asm string from td file.
|
|
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
|
|
// LPC0:
|
|
|
|
// add r0, pc, r0
|
|
|
|
// This adds the address of LPC0 to r0.
|
|
|
|
|
|
|
|
// Emit the label.
|
|
|
|
// FIXME: MOVE TO SHARED PLACE.
|
2009-10-19 22:33:05 +00:00
|
|
|
unsigned Id = (unsigned)MI->getOperand(2).getImm();
|
2009-10-19 22:49:00 +00:00
|
|
|
const char *Prefix = MAI->getPrivateGlobalPrefix();
|
2009-11-06 22:24:13 +00:00
|
|
|
MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
|
|
|
|
+ "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
|
2009-10-19 22:49:00 +00:00
|
|
|
OutStreamer.EmitLabel(Label);
|
2009-10-19 22:23:04 +00:00
|
|
|
|
|
|
|
|
|
|
|
// Form and emit tha dd.
|
|
|
|
MCInst AddInst;
|
|
|
|
AddInst.setOpcode(ARM::ADDrr);
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
|
|
|
printMCInst(&AddInst);
|
|
|
|
return;
|
|
|
|
}
|
2009-10-19 22:33:05 +00:00
|
|
|
case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
|
|
|
|
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
|
|
|
|
/// in the function. The first operand is the ID# for this instruction, the
|
|
|
|
/// second is the index into the MachineConstantPool that this is, the third
|
|
|
|
/// is the size in bytes of this constant pool entry.
|
|
|
|
unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
|
|
|
|
unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
|
|
|
|
|
|
|
|
EmitAlignment(2);
|
|
|
|
|
2009-10-19 22:51:16 +00:00
|
|
|
const char *Prefix = MAI->getPrivateGlobalPrefix();
|
|
|
|
MCSymbol *Label = OutContext.GetOrCreateSymbol(Twine(Prefix)+"CPI"+
|
|
|
|
Twine(getFunctionNumber())+
|
|
|
|
"_"+ Twine(LabelId));
|
|
|
|
OutStreamer.EmitLabel(Label);
|
2009-10-19 22:33:05 +00:00
|
|
|
|
|
|
|
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
|
|
|
|
if (MCPE.isMachineConstantPoolEntry())
|
|
|
|
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
|
|
|
|
else
|
|
|
|
EmitGlobalConstant(MCPE.Val.ConstVal);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
2009-10-20 00:40:56 +00:00
|
|
|
case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
|
|
|
|
// This is a hack that lowers as a two instruction sequence.
|
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
|
|
|
|
|
|
|
|
unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
|
|
|
|
unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
|
|
|
|
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVi);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
|
|
|
|
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
2009-10-20 00:46:11 +00:00
|
|
|
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
|
2009-10-20 00:40:56 +00:00
|
|
|
printMCInst(&TmpInst);
|
|
|
|
O << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::ORRri);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
|
|
|
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
|
|
|
|
printMCInst(&TmpInst);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2009-10-20 01:11:37 +00:00
|
|
|
case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
|
|
|
|
// This is a hack that lowers as a two instruction sequence.
|
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
|
|
|
|
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVi16);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
|
|
|
|
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
|
|
|
|
|
|
|
printMCInst(&TmpInst);
|
|
|
|
O << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVTi16);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
|
|
|
|
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
|
|
|
|
|
|
|
printMCInst(&TmpInst);
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
2009-10-19 20:20:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MCInst TmpInst;
|
|
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
|
|
|
|
|
|
printMCInst(&TmpInst);
|
|
|
|
}
|
2009-10-20 05:15:36 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Target Registry Stuff
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
static MCInstPrinter *createARMMCInstPrinter(const Target &T,
|
|
|
|
unsigned SyntaxVariant,
|
|
|
|
const MCAsmInfo &MAI,
|
|
|
|
raw_ostream &O) {
|
|
|
|
if (SyntaxVariant == 0)
|
|
|
|
return new ARMInstPrinter(O, MAI, false);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Force static initialization.
|
|
|
|
extern "C" void LLVMInitializeARMAsmPrinter() {
|
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
|
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
|
|
|
|
|
|
|
|
TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
|
|
|
|
TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
|
|
|
|
}
|
|
|
|
|